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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2019-07-02 17:13:19 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-09-04 10:57:03 +0000
commit31d04e6e0dd6105f67a28a42634c806a548d8930 (patch)
tree256b1d46f38173ba8d728f17c654b8aeaa84681f /src/mainboard/amd/padmelon/gpio.c
parentfb6ea0af4015ba7d0fef49af833d3b1c19796b38 (diff)
downloadcoreboot-31d04e6e0dd6105f67a28a42634c806a548d8930.tar.xz
mainboard/amd: Add padmelon board code
Padmelon board code was written for Merlin Falcon (family 15h models 60h-6fh), but as the needed binaries are not yet merged (commit 33615), a config HAVE_MERLINFALCON_BINARIES was added. If the binaries are not available, the board defaults to Prairie Falcon, which use the same binaries as Stoney Ridge. Once the binaries are merged, the config will be eliminated. Fan control is done through F81803A SIO, and IRQ/GPIO and other board characteristics are the same regardless of Merlin Falcon or Prairie Falcon. Padmelon board was created to accept Prairie Falcon, Brown Falcon and Merlin Falcon. The requested development was for Merlin Falcon. There are some small spec changes (such as number of memory channels) between SOCs. Brown Falcon was not investigated, Prairie Falcon is very similar to Stoney Ridge. Started from Gardenia code, added changes created by Marc Jones and finally revised against schematic, which added changes to GPIO settings. BUG=none. TEST=Both versions tested and boot to Linux using SeaBIOS. Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/amd/padmelon/gpio.c')
-rw-r--r--src/mainboard/amd/padmelon/gpio.c67
1 files changed, 67 insertions, 0 deletions
diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c
new file mode 100644
index 0000000000..e738618924
--- /dev/null
+++ b/src/mainboard/amd/padmelon/gpio.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <amdblocks/agesawrapper.h>
+#include <amdblocks/BiosCallOuts.h>
+#include <soc/southbridge.h>
+#include <stdlib.h>
+#include "gpio.h"
+
+/*
+ * As a rule of thumb, GPIO pins used by coreboot should be initialized at
+ * bootblock while GPIO pins used only by the OS should be initialized at
+ * ramstage.
+ */
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+ /* GFX presense detect */
+ PAD_GPI(GPIO_9, PULL_DOWN),
+ /* VDDP_VCTRL */
+ PAD_GPO(GPIO_40, HIGH),
+ /* PC SPKR */
+ PAD_NF(GPIO_91, SPKR, PULL_NONE),
+};
+
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
+#if CONFIG(HAVE_S3_SUPPORT)
+ /* PCIE_WAKE - default, do not program */
+
+ /* DEVSLP1 */
+ PAD_NF(GPIO_70, DEVSLP1, PULL_UP),
+ /* WLAND */
+ PAD_SCI(GPIO_137, PULL_UP, LEVEL_LOW),
+ PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3),
+#else
+ /* PCIE_WAKE */
+ PAD_GPI(GPIO_2, PULL_DOWN),
+ /* DEVSLP1 - default as GPIO, do not program */
+
+ /* WLAND - default as GPIO, do not program */
+
+#endif /* HAVE_S3_SUPPORT */
+ /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */
+ PAD_GPO(GPIO_11, HIGH),
+};
+
+const struct soc_amd_gpio *early_gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_reset);
+ return gpio_set_stage_reset;
+}
+
+const struct soc_amd_gpio *gpio_table(size_t *size)
+{
+ *size = ARRAY_SIZE(gpio_set_stage_ram);
+ return gpio_set_stage_ram;
+}