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author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-08-07 12:19:10 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2018-08-09 15:56:32 +0000 |
commit | 08fc8fff255c3aa27362655887a5f5bcd786857c (patch) | |
tree | 3947fb4c6ac77a6e357cd8968f7159d0c5888a47 /src/mainboard/amd/persimmon/mainboard.c | |
parent | 2f79eb3fd567b7578378c4acbecaf2502d1982f4 (diff) | |
download | coreboot-08fc8fff255c3aa27362655887a5f5bcd786857c.tar.xz |
src/mainboard: Fix typo
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/persimmon/mainboard.c')
-rw-r--r-- | src/mainboard/amd/persimmon/mainboard.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index c21e0eac55..95aec3deb9 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -85,7 +85,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { */ /* * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H - * but because PCI INT_PIN swizzling isnt implemented to match + * but because PCI INT_PIN swizzling isn't implemented to match * the IDSEL (dev 3) of the slot, the table is adjusted for the * swizzle and INTA is connected to PIRQH so PINA/B/C/D on * off-chip devices should get mapped to PIRQH/E/F/G. |