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authorScott Duplichan <scott@notabs.org>2011-05-15 22:07:56 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 22:07:56 +0000
commita64ab46b629737658a461914d0d63ae713c0e760 (patch)
tree63b05f32b07d0c5759cf04b7c12334dc1d8b7469 /src/mainboard/amd/persimmon
parent769527e523bb40ecb33a1f6811dae0d689ca4e26 (diff)
downloadcoreboot-a64ab46b629737658a461914d0d63ae713c0e760.tar.xz
Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/persimmon')
-rw-r--r--src/mainboard/amd/persimmon/devicetree.cb14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index 8ca165b739..3a9ec400a6 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -81,13 +81,13 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
end
end # f81865f
end #LPC
- device pci 14.4 on end # PCI 0x4384
- device pci 14.5 on end # USB 2
- device pci 15.0 on end # PCIe PortA
- device pci 15.1 on end # PCIe PortB
- device pci 15.2 on end # PCIe PortC
- device pci 15.3 on end # PCIe PortD
- register "gpp_configuration" = "4" #1:1:1:1
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 2
+ device pci 15.0 off end # PCIe PortA
+ device pci 15.1 off end # PCIe PortB
+ device pci 15.2 off end # PCIe PortC
+ device pci 15.3 off end # PCIe PortD
+ register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx_wrapper/sb800
# end # device pci 18.0