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authorScott Duplichan <scott@notabs.org>2011-05-15 21:54:04 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 21:54:04 +0000
commit2cc5f550c72ac6a13da798b8f073e3d5c55177e0 (patch)
tree3e024874a10cd2f84f3d78554b6a6aa856ef0295 /src/mainboard/amd/persimmon
parentd9a634c7560d0af50e141ad18ffc8c48519209e7 (diff)
downloadcoreboot-2cc5f550c72ac6a13da798b8f073e3d5c55177e0.tar.xz
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/persimmon')
-rw-r--r--src/mainboard/amd/persimmon/romstage.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index e3ed847fdb..da2db64071 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
+ // early enable of PrefetchEnSPIFromHost
+ if (boot_cpu())
+ {
+ __outdword (0xcf8, 0x8000a3b8);
+ __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+ }
+
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{