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| author | Zheng Bao <zheng.bao@amd.com> | 2009-10-16 07:44:04 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-10-16 07:44:04 +0000 |
| commit | 289a2f5aad4eb8b231083ce4250bc382dad6cdbc (patch) | |
| tree | acc88f778d55d6e437fa606a846b337664ffe6ad /src/mainboard/amd/pistachio/Config.lb | |
| parent | 9d37532bc1075360c3f1eca8f000afd7c178de5a (diff) | |
| download | coreboot-289a2f5aad4eb8b231083ce4250bc382dad6cdbc.tar.xz | |
Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the
VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom
to make the final image with vga bios.
The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.
## Index: src/southbridge/amd/rs690/chip.h
## ===================================================================
## --- src/southbridge/amd/rs690/chip.h (revision 4782)
## +++ src/southbridge/amd/rs690/chip.h (working copy)
## @@ -23,7 +23,6 @@
## /* Member variables are defined in Config.lb. */
## struct southbridge_amd_rs690_config
## {
## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */
## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
##
Don't apply above patch about rs690/chip.h before every board has been fixed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/pistachio/Config.lb')
| -rw-r--r-- | src/mainboard/amd/pistachio/Config.lb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb index e0458d3609..b0f82b21c7 100644 --- a/src/mainboard/amd/pistachio/Config.lb +++ b/src/mainboard/amd/pistachio/Config.lb @@ -136,7 +136,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -171,7 +170,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" |