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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-24 18:18:20 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-24 18:18:20 +0000 |
| commit | b015d02a857b27a65a3ef52839361236645754d2 (patch) | |
| tree | 25f3b2b53a2d9dc4e91b1fd2004ed9454d325344 /src/mainboard/amd/pistachio | |
| parent | 8a6163e02b7fcbbeb0d3e88569a5df8bc3c7b072 (diff) | |
| download | coreboot-b015d02a857b27a65a3ef52839361236645754d2.tar.xz | |
Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.
Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/pistachio')
| -rw-r--r-- | src/mainboard/amd/pistachio/romstage.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 182fab8a0b..a3909f4799 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -46,6 +46,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#if CONFIG_USBDEBUG +#include "southbridge/amd/sb600/sb600_enable_usbdebug.c" +#include "pc80/usbdebug_serial.c" +#endif + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -117,8 +122,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); /* Pistachio used a FPGA to enable serial debug instead of a SIO - * and it doens't require any special setup. */ + * and it doesn't require any special setup. */ uart_init(); + +#if CONFIG_USBDEBUG + sb600_enable_usbdebug(0); + early_usbdebug_init(); +#endif + console_init(); post_code(0x03); |