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authorStefan Reinauer <stepan@coresystems.de>2010-04-15 12:39:29 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-15 12:39:29 +0000
commit23836e2345282151b0b46de6cdcd2bb2faee87f6 (patch)
treee1e416ae11a78b455a26f378f33d0a8db6fa69af /src/mainboard/amd/pistachio
parentc30a6e859e20dbadbad006f2f93068e7f9c36043 (diff)
downloadcoreboot-23836e2345282151b0b46de6cdcd2bb2faee87f6.tar.xz
zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/pistachio')
-rw-r--r--src/mainboard/amd/pistachio/mainboard.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index be36458204..d1d9a849fc 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <../southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7475_ADDRESS 0x2E
@@ -35,9 +34,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
-
#define ADT7475_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
#define ADT7475_write_byte(address, val) \