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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 16:46:50 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 16:46:50 +0000
commit2bd91003413d431f0a4db6c3c6691f4b688cf5c5 (patch)
tree87928431192b8fea7b5dbc3a32dc67283237d66d /src/mainboard/amd/pistachio
parent776b85ba457ff82f795c6c65b5574ef27e611097 (diff)
downloadcoreboot-2bd91003413d431f0a4db6c3c6691f4b688cf5c5.tar.xz
Rework boolean expression (DeMorgan and all) for
better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/pistachio')
-rw-r--r--src/mainboard/amd/pistachio/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 0db2f3413b..3af55eed92 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+ if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();