summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/pistachio
diff options
context:
space:
mode:
authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 09:43:25 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 09:43:25 +0000
commit513e03bd96b9c2d2c3a9ad10961de4f76586ace3 (patch)
tree1e355e1912744adb43d25a9896388907e5b071d7 /src/mainboard/amd/pistachio
parent00003ae7129802d7f943756c94b35372c1b1b053 (diff)
downloadcoreboot-513e03bd96b9c2d2c3a9ad10961de4f76586ace3.tar.xz
r4646 enabled early usage of pci_{read,write}_config{8,16,32}
This allows us to change dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); to the much more readable dword = pci_read_config32(sm_dev, 0x64); Clean up all PCI operations in mainboards based on AMD 690: amd/pistachio amd/dbm690t technexion/tim8690 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/pistachio')
-rw-r--r--src/mainboard/amd/pistachio/mainboard.c29
1 files changed, 8 insertions, 21 deletions
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index c7c539b887..090f9b7dc3 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -83,7 +83,6 @@ static void set_thermal_config()
u16 word;
u32 dword;
device_t sm_dev;
- struct bus pbus;
/* set adt7475 */
ADT7475_write_byte(0x40, 0x04);
@@ -167,28 +166,19 @@ static void set_thermal_config()
/* GPM5 as GPIO not USB OC */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- dword =
- pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x64);
+ dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 19;
- pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x64, dword);
+ pci_write_config32(sm_dev, 0x64, dword);
/* Enable Client Management Index/Data registers */
- dword =
- pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x78);
+ dword = pci_read_config32(sm_dev, 0x78);
dword |= 1 << 11; /* Cms_enable */
- pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x78, dword);
+ pci_write_config32(sm_dev, 0x78, dword);
/* MiscfuncEnable */
- byte =
- pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x41);
+ byte = pci_read_config8(sm_dev, 0x41);
byte |= (1 << 5);
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x41, byte);
+ pci_write_config8(sm_dev, 0x41, byte);
/* set GPM5 as input */
/* set index register 0C50h to 13h (miscellaneous control) */
@@ -228,12 +218,9 @@ static void set_thermal_config()
pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */
- word =
- pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56);
+ word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
- pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56, word);
+ pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);