diff options
author | Stefan Reinauer <stepan@openbios.org> | 2003-10-24 14:45:21 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2003-10-24 14:45:21 +0000 |
commit | 888df97971271655a2b3cacf96d509dadf15fd85 (patch) | |
tree | 6df45cfd0f5ea283b993d2d14f65848eaee2e335 /src/mainboard/amd/quartet/auto.c | |
parent | e4436bd7f640170c03798914baa2c47690df5e61 (diff) | |
download | coreboot-888df97971271655a2b3cacf96d509dadf15fd85.tar.xz |
merge latest quartet changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/quartet/auto.c')
-rw-r--r-- | src/mainboard/amd/quartet/auto.c | 49 |
1 files changed, 33 insertions, 16 deletions
diff --git a/src/mainboard/amd/quartet/auto.c b/src/mainboard/amd/quartet/auto.c index 23951738c6..d7507fd12d 100644 --- a/src/mainboard/amd/quartet/auto.c +++ b/src/mainboard/amd/quartet/auto.c @@ -19,25 +19,32 @@ #include "cpu/p6/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "debug.c" +#include "northbridge/amd/amdk8/cpu_rev.c" #define SIO_BASE 0x2e static void memreset_setup(void) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30); - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31); + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } + else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + } } static void memreset(int controllers, const struct mem_controller *ctrl) { - udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); - udelay(90); + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } } /* @@ -110,9 +117,6 @@ static void coherent_ht_mainboard(unsigned cpus) { } -#include "northbridge/amd/amdk8/cpu_ldtstop.c" -#include "southbridge/amd/amd8111/amd8111_ldtstop.c" - #include "northbridge/amd/amdk8/raminit.c" #define CONNECTION_0_1 UP @@ -272,8 +276,21 @@ static void main(void) #endif #if 0 ram_check(0x00000000, msr.lo); -#else - /* Check 16MB of memory */ - ram_check(0x00000000, 0x01000000); +#endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if 0 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } #endif } |