summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/quartet
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@openbios.org>2004-10-21 17:06:49 +0000
committerStefan Reinauer <stepan@openbios.org>2004-10-21 17:06:49 +0000
commita49f4161f5631760309ba47b925183736a754717 (patch)
tree34175ea6c904dc857fdb353407bef66116bcf748 /src/mainboard/amd/quartet
parentdbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d (diff)
downloadcoreboot-a49f4161f5631760309ba47b925183736a754717.tar.xz
update failover handling of some amd64 boards
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/quartet')
-rw-r--r--src/mainboard/amd/quartet/failover.c65
1 files changed, 46 insertions, 19 deletions
diff --git a/src/mainboard/amd/quartet/failover.c b/src/mainboard/amd/quartet/failover.c
index e40891b50d..e351cae83d 100644
--- a/src/mainboard/amd/quartet/failover.c
+++ b/src/mainboard/amd/quartet/failover.c
@@ -3,40 +3,67 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
-#include "arch/romcc_io.h"
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-static void main(void)
+static unsigned long main(unsigned long bist)
{
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
+ /* Make cerain my local apic is useable */
+ enable_lapic();
- /* Is this a cpu reset? */
+ /* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
- asm("jmp __normal_image");
+ goto normal_image;
} else {
- asm("jmp __cpu_reset");
+ goto cpu_reset;
}
}
- /* Is this a deliberate reset by the bios */
- else if (bios_reset_detected() && last_boot_normal()) {
- asm("jmp __normal_image");
- }
/* Is this a secondary cpu? */
- else if (!boot_cpu() && last_boot_normal()) {
- asm("jmp __normal_image");
+ if (!boot_cpu()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+
+ /* Setup the 8111 */
+ amd8111_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
- asm("jmp __normal_image");
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
}
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
}