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authorMartin Roth <gaumless@gmail.com>2017-10-15 14:16:37 -0600
committerMartin Roth <martinroth@google.com>2018-01-15 23:22:59 +0000
commit99c45dee0ae62254be36a312d67764784450b564 (patch)
tree193b20bb742056464374373ba65b07bc901f07c7 /src/mainboard/amd/rumba/devicetree.cb
parentb94b2c73068eba434cdd162fac1d50cf22524259 (diff)
downloadcoreboot-99c45dee0ae62254be36a312d67764784450b564.tar.xz
AMD GX2 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/amd/rumba/devicetree.cb')
-rw-r--r--src/mainboard/amd/rumba/devicetree.cb20
1 files changed, 0 insertions, 20 deletions
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb
deleted file mode 100644
index d48035521c..0000000000
--- a/src/mainboard/amd/rumba/devicetree.cb
+++ /dev/null
@@ -1,20 +0,0 @@
-chip northbridge/amd/gx2
- device cpu_cluster 0 on
- chip cpu/amd/geode_gx2
- device lapic 0 on end
- end
- end
- device domain 0 on
- device pci 1.0 on end
- device pci 1.1 on end
- chip southbridge/amd/cs5536
- register "lpc_serirq_enable" = "0x80" # enabled with default timing
- device pci d.0 on end # Realtek 8139 LAN
- device pci f.0 on end # ISA Bridge
- device pci f.2 on end # IDE Controller
- device pci f.3 on end # Audio
- device pci f.4 on end # OHCI
- device pci f.5 on end # EHCI
- end
- end
-end