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author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-27 21:56:36 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-09-28 22:15:40 +0200 |
commit | eeabb75e8c5a72fb01c1966fd91ea398818f15b3 (patch) | |
tree | f5514c6fc75e457399630bbfcafe395b7c5aca66 /src/mainboard/amd/rumba/devicetree.cb | |
parent | 39aa6309ba2c356c3e51640ce454ef37d5976f31 (diff) | |
download | coreboot-eeabb75e8c5a72fb01c1966fd91ea398818f15b3.tar.xz |
mainboard/amd/rumba: Use tabs for indents
Change-Id: I005e607faa2a6c527584ba9cdcad92f4517a15e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16778
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/amd/rumba/devicetree.cb')
-rw-r--r-- | src/mainboard/amd/rumba/devicetree.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index 62fb28735e..d48035521c 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -4,17 +4,17 @@ chip northbridge/amd/gx2 device lapic 0 on end end end - device domain 0 on - device pci 1.0 on end + device domain 0 on + device pci 1.0 on end device pci 1.1 on end - chip southbridge/amd/cs5536 + chip southbridge/amd/cs5536 register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI - end - end + end + end end |