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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 20:05:38 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-25 20:05:38 +0000 |
| commit | 417d8c44f959128aa345b332e7b8296834623c67 (patch) | |
| tree | 5b7c43679082d71b8c83f3903d30b70c0154a2dc /src/mainboard/amd/rumba | |
| parent | cf120d1a89e81b3bb3c4a201a759054ccc006919 (diff) | |
| download | coreboot-417d8c44f959128aa345b332e7b8296834623c67.tar.xz | |
set irq options.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/rumba')
| -rw-r--r-- | src/mainboard/amd/rumba/Config.lb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb index a7962f51d0..d99f74793f 100644 --- a/src/mainboard/amd/rumba/Config.lb +++ b/src/mainboard/amd/rumba/Config.lb @@ -133,6 +133,9 @@ chip northbridge/amd/gx2 device pci 1.0 on end device pci 1.1 on end chip southbridge/amd/cs5536 + register "lpc_serirq_enable" = "0x80" # enabled with default timing + register "lpc_irq" = "((1<<3)|(1<<4))" # IRQ 3 & 4 + register "enable_gpio0_inta" = "1" device pci d.0 on end # Realtek 8139 LAN device pci f.0 on end # ISA Bridge device pci f.2 on end # IDE Controller |