diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-07-26 23:46:25 +0000 |
|---|---|---|
| committer | Joseph Smith <joe@smittys.pointclark.net> | 2010-07-26 23:46:25 +0000 |
| commit | e474070bdd3410fef471a7a142453a883a9f7793 (patch) | |
| tree | 578d9a74c2bcddee89bd7db21ea9fb5bcff00a4e /src/mainboard/amd/rumba | |
| parent | e3fb1c2531573ca246221167156721e40c3ef47c (diff) | |
| download | coreboot-e474070bdd3410fef471a7a142453a883a9f7793.tar.xz | |
This patch converts the Geode GX2 boards to CAR.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/rumba')
| -rw-r--r-- | src/mainboard/amd/rumba/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/amd/rumba/romstage.c | 22 |
2 files changed, 7 insertions, 18 deletions
diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index 98bea7e33c..3a76969a55 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -23,8 +23,9 @@ config BOARD_AMD_RUMBA select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index ca2aac9cd5..120720f77a 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -99,22 +98,9 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - /* total physical memory */ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - /* traditional memory 0kB-512kB, 512kB-1MB */ - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); +#include "cpu/amd/model_lx/msrinit.c" - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - - /* put code in northbridge[init].c here */ -} - -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -122,13 +108,15 @@ static void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); cs5536_early_setup(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); |