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| author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:09:09 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 23:09:09 +0000 |
| commit | d95465d08f5be0ec46fe3b1f801b98f7c5a43f81 (patch) | |
| tree | 2856a07deb731a3ef6ee136baa3cfda8cf0739bd /src/mainboard/amd/serengeti_cheetah/dx/pci3.asl | |
| parent | 31ed8983c3a87856c89791561e2a281beedfb3ba (diff) | |
| download | coreboot-d95465d08f5be0ec46fe3b1f801b98f7c5a43f81.tar.xz | |
add missed asl for ht chain
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah/dx/pci3.asl')
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah/dx/pci3.asl | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl b/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl new file mode 100644 index 0000000000..1507cfc0f9 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/dx/pci3.asl @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci3_hc.asl") + } + } + +} + |