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author | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
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committer | Yinghai Lu <yinghailu@gmail.com> | 2006-10-04 20:46:15 +0000 |
commit | d4b278c02c1da92219ebeb34204b9768934aeca3 (patch) | |
tree | 488d097cac9744cfc9b8ff7c89ce69bcb21370cb /src/mainboard/amd/serengeti_cheetah/irq_tables.c | |
parent | 2e3757d11c565a8fe68dc2a2c34975e98304533c (diff) | |
download | coreboot-d4b278c02c1da92219ebeb34204b9768934aeca3.tar.xz |
AMD Rev F support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah/irq_tables.c')
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah/irq_tables.c | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c new file mode 100644 index 0000000000..fb793078df --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -0,0 +1,139 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdk8_sysconf.h> + +#include "mb_sysconf.h" + +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +extern void get_bus_conf(void); + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + unsigned slot_num; + uint8_t *v; + + uint8_t sum=0; + int i; + + struct mb_sysconf_t *m; + + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + + m = sysconf.mb; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk_info("Writing IRQ routing tables to 0x%x...", addr); + + pirq = (void *)(addr); + v = (uint8_t *)(addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = m->bus_8111_0; + pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1022; + pirq->rtr_device = 0x746b; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *) ( &pirq->checksum + 1); + slot_num = 0; + + { + device_t dev; + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ3 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ11 + */ + pci_write_config16(dev, 0x56, 0xba53); + } + } + +//pci bridge + printk_debug("setting Onboard AMD Southbridge \n"); + static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; + pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); + write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + + printk_debug("setting Onboard AMD USB \n"); + static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; + pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); + write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + +//pcix bridge +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++; + + if(sysconf.pci1234[1] & 0xf) { + //agp bridge + write_pirq_info(pirq_info, m->bus_8151_0, (m->sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + } + + pirq_info++; slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk_info("done.\n"); + + return (unsigned long) pirq_info; + +} |