src/mainboard/a-trend - emulation: Add space around operators

Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

5 files changed, 36 insertions, 36 deletions

diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
index f75f8208f6..ddc232f03f 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
@@ -37,7 +37,7 @@
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-	u32 gsi_base=0x18;
+	u32 gsi_base = 0x18;
 
 	struct mb_sysconf_t *m;
 
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 		int i;
 		int j = 0;
 
-		for(i=1; i< sysconf.hc_possible_num; i++) {
+		for(i = 1; i< sysconf.hc_possible_num; i++) {
 			u32 d = 0;
 			if(!(sysconf.pci1234[i] & 0x1) ) continue;
 			// 8131 need to use +4
@@ -149,11 +149,11 @@ unsigned long mainboard_write_acpi_tables(device_t dev, unsigned long start, acp
 
 	//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
 
-	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+	for(i = 1; i < sysconf.hc_possible_num; i++) {  // 0: is hc sblink
 		const char *file_name;
 		if((sysconf.pci1234[i] & 1) != 1 ) continue;
 		u8 c;
-		if(i<7) {
+		if(i < 7) {
 			c  = (u8) ('4' + i - 1);
 		}
 		else {
diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c
index bd0096152b..6bb03e92e7 100644
--- a/src/mainboard/amd/serengeti_cheetah/fadt.c
+++ b/src/mainboard/amd/serengeti_cheetah/fadt.c
@@ -37,13 +37,13 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
 	memcpy(header->oem_id,OEM_ID,6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id,ASLC,4);
-	header->asl_compiler_revision=0;
+	header->asl_compiler_revision = 0;
 
 	fadt->firmware_ctrl=(u32)facs;
 	fadt->dsdt= (u32)dsdt;
-	// 3=Workstation,4=Enterprise Server, 7=Performance Server
-	fadt->preferred_pm_profile=0x03;
-	fadt->sci_int=9;
+	// 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
 	// disable system management mode by setting to 0:
 	fadt->smi_cmd = 0;//pm_base+0x2f;
 	fadt->acpi_enable = 0xf0;
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
index 2fc3ee6334..3d9820f542 100644
--- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c
+++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c
@@ -124,7 +124,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	slot_num++;
 
 //pcix bridge
-//        write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+//        write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 //        pirq_info++; slot_num++;
 
 	int j = 0;
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 8236e7baa3..acc4a6c68c 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v)
 
                 j = 0;
 
-                for(i=1; i< sysconf.hc_possible_num; i++) {
+                for(i = 1; i< sysconf.hc_possible_num; i++) {
                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
 
                         switch(sysconf.hcid[i]) {
@@ -101,34 +101,34 @@ static void *smp_write_config_table(void *v)
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 
 // Onboard AMD USB
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0 << 2)|3, m->apicid_8111, 0x13);
 
 //Slot 3  PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5 << 2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
         }
 
 
 //Slot 4 PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4 << 2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
         }
 
 
 //Slot 1 PCI-X 133/100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1 << 2)|i, m->apicid_8132_2, (0+i)%4); //
         }
 
 
 //Slot 2 PCI-X 133/100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
+        for(i = 0; i < 4; i++) {
+                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1 << 2)|i, m->apicid_8132_1, (1+i)%4); //25
         }
 
         j = 0;
 
-        for(i=1; i< sysconf.hc_possible_num; i++) {
+        for(i = 1; i< sysconf.hc_possible_num; i++) {
                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
                 int ii;
                 device_t dev;
@@ -141,8 +141,8 @@ static void *smp_write_config_table(void *v)
                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
                                 if (res) {
                                         //Slot 1 PCI-X 133/100/66
-                                        for(ii=0;ii<4;ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+                                        for(ii = 0; ii < 4; ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0 << 2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
                                         }
                                 }
                         }
@@ -152,8 +152,8 @@ static void *smp_write_config_table(void *v)
                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
                                 if (res) {
                                         //Slot 2 PCI-X 133/100/66
-                                        for(ii=0;ii<4;ii++) {
-                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+                                        for(ii = 0; ii < 4; ii++) {
+                                                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0 << 2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
                                         }
                                 }
                         }
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 51fce316a7..53adf6c274 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -38,8 +38,8 @@
 static void memreset_setup(void)
 {
 	//GPIO on amd8111 to enable MEMRST ????
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-        outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+        outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN = 1
+        outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -49,11 +49,11 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
 #define SMBUS_HUB 0x18
         int ret,i;
         unsigned device=(ctrl->channel0[0])>>8;
-        /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-        i=2;
+        /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+        i = 2;
         do {
                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-        } while ((ret!=0) && (i-->0));
+        } while ((ret != 0) && (i-->0));
 
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
@@ -74,10 +74,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#define RC0 ((1<<0)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<2)<<8)
-#define RC3 ((1<<3)<<8)
+#define RC0 ((1 << 0)<<8)
+#define RC1 ((1 << 1)<<8)
+#define RC2 ((1 << 2)<<8)
+#define RC3 ((1 << 3)<<8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         {
 		/* Read FIDVID_STATUS */
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         // show final fid and vid
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -200,7 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if 0
 	int i;
-	for(i=0;i<4;i++) {
+	for(i = 0; i < 4; i++) {
 		activate_spd_rom(&cpu[i]);
 		dump_smbus_registers();
 	}