Kconfig!

Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 303 insertions, 0 deletions

diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig
new file mode 100644
index 0000000000..bb1571de95
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/Kconfig
@@ -0,0 +1,49 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_AMD
+
+config BOARD_AMD_SERENGETI_CHEETAH
+	bool "SERENGETI_CHEETAH"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_F
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_AMD8111
+	select SUPERIO_WINBOND_W83627THF
+	select PIRQ_TABLE
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+	help
+	AMD Serengeti Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default amd/serengeti_cheetah
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffdf8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+#	
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Serengeti-Cheetah"
+	depends on BOARD_AMD_SERENGETI_CHEETAH
diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc
new file mode 100644
index 0000000000..c54df30683
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc
@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=1 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1 \
+	-DCONFIG_MMCONF_SUPPORT=1 \
+	-DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+           
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
new file mode 100644
index 0000000000..b9742b4a46
--- /dev/null
+++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb
@@ -0,0 +1,159 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
+                                                        device i2c 18 on #0 pca9516 1
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 18 on #1 pca9516 2
+                                                                chip drivers/generic/generic #dimm 1-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                        end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+                	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+                        device pci 18.0 on end
+                        device pci 18.0 on end  
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+                chip northbridge/amd/amdk8
+                        device pci 19.0 on #  northbridge
+                                chip southbridge/amd/amd8151
+                                        # the on/off keyword is mandatory
+                                        device pci 0.0 on end
+                                        device pci 1.0 on end
+                                end
+                        end #  device pci 19.0
+
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.1 on end
+                        device pci 19.2 on end
+                        device pci 19.3 on end
+                end
+
+
+	end #pci_domain
+#        chip drivers/generic/debug
+#        	device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+
+