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authorStefan Reinauer <stepan@coresystems.de>2008-01-18 15:08:58 +0000
committerStefan Reinauer <stepan@openbios.org>2008-01-18 15:08:58 +0000
commitf8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch)
tree7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/mainboard/amd/serengeti_cheetah
parent7e61e45402aba2b90997f4f02ca8266cf65a229a (diff)
downloadcoreboot-f8ee1806ac524bc782c93eccc59ee3c929abddb9.tar.xz
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah')
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Config.lb14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/Options.lb14
-rw-r--r--src/mainboard/amd/serengeti_cheetah/readme_acpi.txt8
3 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
index f54c423fbd..6948a70948 100644
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Config.lb
@@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FAILOVER_IMAGE
default ROM_SECTION_SIZE = FAILOVER_SIZE
@@ -17,18 +17,18 @@ end
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@@ -154,7 +154,7 @@ else
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if HAVE_FAILOVER_BOOT
@@ -181,7 +181,7 @@ if USE_DCACHE_RAM
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@@ -215,7 +215,7 @@ if USE_DCACHE_RAM
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
index 0b2f24e991..9cdc29dac9 100644
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ b/src/mainboard/amd/serengeti_cheetah/Options.lb
@@ -40,7 +40,7 @@ uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
@@ -122,7 +122,7 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_FAILOVER_BOOT=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=1
@@ -149,7 +149,7 @@ default ACPI_SSDTX_NUM=1
default HAVE_OPTION_TABLE=1
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Move the default coreboot cmos range off of AMD RTC registers
##
default LB_CKS_RANGE_START=49
default LB_CKS_RANGE_END=122
@@ -237,10 +237,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
##
@@ -259,7 +259,7 @@ default HEAP_SIZE=0x8000
default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
##
-## LinuxBIOS C code runs at this location in RAM
+## Coreboot C code runs at this location in RAM
##
default _RAMBASE=0x00100000
@@ -309,7 +309,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
index 2fb327daec..99a89f94e4 100644
--- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
+++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt
@@ -1,7 +1,7 @@
At this time, For acpi support We got
-1. support AMK K8 SRAT --- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
-2. support MADT ---- dynamically (LinuxBIOS run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
-3. support DSDT ---- dynamically (Compile time, LinuxBIOS run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
+1. support AMK K8 SRAT --- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c)
+2. support MADT ---- dynamically (coreboot run-time) (src/northbridge/amd/amdk8/amdk8_acpi.c , src/mainboard/amd/serengeti_cheetah/acpi_tables.c)
+3. support DSDT ---- dynamically (Compile time, coreboot run-time, ACPI run-time) (src/mainboard/amd/serengeti_cheetah/{dx/*, get_bus_conf.c}, src/northbridge/amd/amdk8/get_sblk_pci1234.c)
4. Chipset support: amd8111, amd8132
The developers need to change for different MB
@@ -11,7 +11,7 @@ Change dx/dsdt_lb.dsl, according to MB layout
if there is HT-IO board, may use pci2.asl.... to create ssdt2.c, and ssdt3,c and ssdt4.c, ....ssdt8.c
Change acpi_tables.c
- sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is LinuxBIOS run-time configurable now.
+ sbdn: Real SB device Num. for 8111 =3 or 1 depend if 8131 presents. ---- Actually you don't need to change it, it is coreboot run-time configurable now.
if there is HT-IO board, need to adjust SSDTX_NUM...., and preset pci1234 array. acpi_tables.c will decide to put the SSDT on the RSDT or not according if the HT-IO board is installed
Regarding pci bridge apic and pic