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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 20:58:41 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 20:58:41 +0000 |
| commit | 78acf932912669eb0eb7f7280da1b3c550035ebb (patch) | |
| tree | 89f13a87df362395527d41f42d0a57a167eab8db /src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | |
| parent | 2bd91003413d431f0a4db6c3c6691f4b688cf5c5 (diff) | |
| download | coreboot-78acf932912669eb0eb7f7280da1b3c550035ebb.tar.xz | |
Remove remaining uses of
HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10/romstage.c')
| -rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 3e9b7a5941..b63dc1099b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -58,7 +58,6 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" @@ -66,7 +65,6 @@ static void post_code(u8 value) { #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #include "cpu/x86/bist.h" -#if (CONFIG_USE_FAILOVER_IMAGE == 0) - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -141,13 +137,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" -#if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -316,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - -#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ |