diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-10 21:25:17 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-10-24 20:31:50 +0200 |
commit | caccd97d4e7700d487a89788eb216e2a5c571204 (patch) | |
tree | a58e96d72e715f785f2c937e6b3847c1a97dab1e /src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | |
parent | 15622ee5f082431bcd927c1137adceaa544ce1ad (diff) | |
download | coreboot-caccd97d4e7700d487a89788eb216e2a5c571204.tar.xz |
mainboard/amd/serengeti_cheetah*: Use C89 comments style & remove commented code
Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10/romstage.c')
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 39 |
1 files changed, 12 insertions, 27 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 1ccdf268c7..fa92219069 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -14,10 +14,8 @@ */ #define SYSTEM_TYPE 0 /* SERVER */ -//#define SYSTEM_TYPE 1 /* DESKTOP */ -//#define SYSTEM_TYPE 2 /* MOBILE */ -//used by incoherent_ht +/* used by incoherent_ht */ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 @@ -50,8 +48,8 @@ static void memreset_setup(void) { - //GPIO on amd8111 to enable MEMRST ???? - outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN = 1 + /* GPIO on amd8111 to enable MEMRST ???? */ + outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); /* REVC_MEMRST_EN = 1 */ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } @@ -87,16 +85,16 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { - //first node + /* first node */ RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + /* second node */ RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node + /* third node */ RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // forth node + /* forth node */ RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 4 @@ -208,12 +206,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); @@ -268,10 +264,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { /* BSP is node 0 */ init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */ } post_code(0x3A); @@ -308,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup(); post_code(0x40); -// die("Die Before MCT init."); - timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -320,18 +314,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); -/* - dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); - dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); -*/ - -// die("After MCT init before CAR disabled."); - post_code(0x42); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x43); // Should never see this post code. + post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */ + post_code(0x43); /* Should never see this post code. */ } /** |