diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/amd/serengeti_cheetah_fam10 | |
parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10')
-rw-r--r-- | src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 17 |
1 files changed, 1 insertions, 16 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index cb5c070f63..4b509b0e74 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -40,25 +40,17 @@ #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> #include <spd.h> - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include <console/loglevel.h> -#if 0 -void die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) -#endif #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" static void memreset_setup(void) { @@ -91,18 +83,14 @@ static int spd_read_byte(u32 device, u32 address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" - #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -201,7 +189,6 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; @@ -353,6 +340,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. - } - |