diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/amd/serengeti_cheetah_fam10 | |
parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
download | coreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/serengeti_cheetah_fam10')
7 files changed, 231 insertions, 231 deletions
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb index 405ebcf4ff..456ad0ecfd 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb @@ -17,8 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -## XIP_ROM_SIZE must be a power of 2. -default XIP_ROM_SIZE = 64 * 1024 +## CONFIG_XIP_ROM_SIZE must be a power of 2. +default CONFIG_XIP_ROM_SIZE = 64 * 1024 include /config/failovercalculation.lb arch i386 end @@ -33,51 +33,51 @@ driver mainboard.o #needed by irq_tables and mptable and acpi_tables object get_bus_conf.o -if HAVE_MP_TABLE +if CONFIG_HAVE_MP_TABLE object mptable.o end -if HAVE_PIRQ_TABLE +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object acpi_tables.o object fadt.o makerule dsdt.c - depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb - if ACPI_SSDTX_NUM + if CONFIG_ACPI_SSDTX_NUM makerule ssdt2.c - depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci2.asl" + action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c - depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci3.asl" + action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c - depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci4.asl" + action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c - depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" + depends "$(CONFIG_MAINBOARD)/dx/pci5.asl" + action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end @@ -88,27 +88,27 @@ end if CONFIG_USE_INIT # compile cache_as_ram.c to auto.o makerule ./cache_as_ram_auto.o - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" end else #compile cache_as_ram.c to auto.inc makerule ./cache_as_ram_auto.inc - depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" action "perl -e 's/\.rodata/.rom.data/g' -pi $@" action "perl -e 's/\.text/.section .rom.text/g' -pi $@" end end -if USE_FAILOVER_IMAGE +if CONFIG_USE_FAILOVER_IMAGE else if CONFIG_AP_CODE_IN_CAR makerule ./apc_auto.o - depends "$(MAINBOARD)/apc_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h" + action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@" end ldscript /arch/i386/init/ldscript_apc.lb end @@ -118,13 +118,13 @@ end ## Build our 16 bit and 32 bit coreboot entry code ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/entry16.inc ldscript /cpu/x86/16bit/entry16.lds end @@ -142,8 +142,8 @@ mainboardinit cpu/x86/32bit/entry32.inc ## ## Build our reset vector (This is where coreboot is entered) ## -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -151,7 +151,7 @@ if HAVE_FAILOVER_BOOT ldscript /cpu/x86/32bit/reset32.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc ldscript /cpu/x86/16bit/reset16.lds else @@ -177,12 +177,12 @@ ldscript /arch/i386/lib/id.lds ### Things are delicate and we test to see if we should ### failover to another image. ### -if HAVE_FAILOVER_BOOT - if USE_FAILOVER_IMAGE +if CONFIG_HAVE_FAILOVER_BOOT + if CONFIG_USE_FAILOVER_IMAGE ldscript /arch/i386/lib/failover_failover.lds end else - if USE_FALLBACK_IMAGE + if CONFIG_USE_FALLBACK_IMAGE ldscript /arch/i386/lib/failover.lds end end diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index c62fbe273e..cd5f586ca7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -17,126 +17,126 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_MP_TABLE +uses CONFIG_HAVE_MP_TABLE uses CONFIG_CBFS -uses HAVE_PIRQ_TABLE -uses HAVE_ACPI_TABLES -uses HAVE_ACPI_RESUME -uses ACPI_SSDTX_NUM -uses USE_FALLBACK_IMAGE -uses USE_FAILOVER_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_FAILOVER_BOOT -uses HAVE_HARD_RESET -uses IRQ_SLOT_COUNT -uses HAVE_OPTION_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_ACPI_RESUME +uses CONFIG_ACPI_SSDTX_NUM +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_USE_FAILOVER_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_FAILOVER_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP -uses FALLBACK_SIZE -uses FAILOVER_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_FALLBACK_SIZE +uses CONFIG_FAILOVER_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses PAYLOAD_SIZE -uses _ROMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses STACK_SIZE -uses HEAP_SIZE -uses USE_OPTION_TABLE -uses LB_CKS_RANGE_START -uses LB_CKS_RANGE_END -uses LB_CKS_LOC -uses MAINBOARD_PART_NUMBER -uses MAINBOARD_VENDOR -uses MAINBOARD -uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_USE_OPTION_TABLE +uses CONFIG_LB_CKS_RANGE_START +uses CONFIG_LB_CKS_RANGE_END +uses CONFIG_LB_CKS_LOC +uses CONFIG_MAINBOARD_PART_NUMBER +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses COREBOOT_EXTRA_VERSION -uses _RAMBASE -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL -uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL +uses CONFIG_RAMBASE +uses CONFIG_TTYS0_BAUD +uses CONFIG_TTYS0_BASE +uses CONFIG_TTYS0_LCS +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 -uses HAVE_INIT_TIMER +uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB uses CONFIG_GDB_STUB -uses CROSS_COMPILE +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN -uses HW_MEM_HOLE_SIZEK -uses HW_MEM_HOLE_SIZE_AUTO_INC - -uses HT_CHAIN_UNITID_BASE -uses HT_CHAIN_END_UNITID_BASE -uses SB_HT_CHAIN_ON_BUS0 -uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE -uses DCACHE_RAM_GLOBAL_VAR_SIZE +uses CONFIG_HW_MEM_HOLE_SIZEK +uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC + +uses CONFIG_HT_CHAIN_UNITID_BASE +uses CONFIG_HT_CHAIN_END_UNITID_BASE +uses CONFIG_SB_HT_CHAIN_ON_BUS0 +uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY + +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE +uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE uses CONFIG_USE_INIT -uses SERIAL_CPU_INIT +uses CONFIG_SERIAL_CPU_INIT -uses ENABLE_APIC_EXT_ID -uses APIC_ID_OFFSET -uses LIFT_BSP_APIC_ID +uses CONFIG_ENABLE_APIC_EXT_ID +uses CONFIG_APIC_ID_OFFSET +uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK -uses PCI_BUS_SEGN_BITS +uses CONFIG_PCI_BUS_SEGN_BITS uses CONFIG_AP_CODE_IN_CAR -uses MEM_TRAIN_SEQ +uses CONFIG_MEM_TRAIN_SEQ -uses WAIT_BEFORE_CPUS_INIT +uses CONFIG_WAIT_BEFORE_CPUS_INIT uses CONFIG_AMDMCT uses CONFIG_USE_PRINTK_IN_CAR -uses CAR_FAM10 -uses AMD_UCODE_PATCH_FILE +uses CONFIG_CAR_FAM10 +uses CONFIG_AMD_UCODE_PATCH_FILE ### ### Build options ### ## -## ROM_SIZE is the size of boot ROM that this board will use. +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## -default ROM_SIZE=1024*1024 +default CONFIG_ROM_SIZE=1024*1024 ## ## #FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#default FALLBACK_SIZE=0x40000 +#default CONFIG_FALLBACK_SIZE=131072 +#default CONFIG_FALLBACK_SIZE=0x40000 #FALLBACK: 1024K - 8K -default FALLBACK_SIZE=0xFE000 +default CONFIG_FALLBACK_SIZE=0xFE000 #FAILOVER: 8k -default FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. @@ -145,42 +145,42 @@ default CONFIG_LB_MEM_TOPK=16384 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=1 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=1 +default CONFIG_HAVE_HARD_RESET=1 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=11 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=11 ## ## Build code to export an x86 MP table ## Useful for specifying IRQ routing values ## -default HAVE_MP_TABLE=1 +default CONFIG_HAVE_MP_TABLE=1 ## ACPI tables will be included -default HAVE_ACPI_TABLES=1 +default CONFIG_HAVE_ACPI_TABLES=1 ## extra SSDT num -default ACPI_SSDTX_NUM=31 +default CONFIG_ACPI_SSDTX_NUM=31 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Move the default coreboot cmos range off of AMD RTC registers ## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 +default CONFIG_LB_CKS_RANGE_START=49 +default CONFIG_LB_CKS_RANGE_END=122 +default CONFIG_LB_CKS_LOC=123 ## ## Build code for SMP support @@ -190,58 +190,58 @@ default CONFIG_MAX_PHYSICAL_CPUS=8 default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS default CONFIG_LOGICAL_CPUS=1 -#default SERIAL_CPU_INIT=0 +#default CONFIG_SERIAL_CPU_INIT=0 -default ENABLE_APIC_EXT_ID=1 -default APIC_ID_OFFSET=0x00 -default LIFT_BSP_APIC_ID=1 +default CONFIG_ENABLE_APIC_EXT_ID=1 +default CONFIG_APIC_ID_OFFSET=0x00 +default CONFIG_LIFT_BSP_APIC_ID=1 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. #2G -#default HW_MEM_HOLE_SIZEK=0x200000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000 #1G -default HW_MEM_HOLE_SIZEK=0x100000 +default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 #512M -#default HW_MEM_HOLE_SIZEK=0x80000 +#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy -#default HW_MEM_HOLE_SIZE_AUTO_INC=1 +#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1 #VGA Console default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 #HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0xa +default CONFIG_HT_CHAIN_UNITID_BASE=0xa #real SB Unit ID, default is 0x20, mean dont touch it at last -default HT_CHAIN_END_UNITID_BASE=0x6 +default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6 #make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 #only offset for SB chain?, default is yes(1) -#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 +#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 #allow capable device use that above 4G #default CONFIG_PCI_64BIT_PREF_MEM=1 #it only be 0, 1, 2, 3, 4 and default is 0 -#default PCI_BUS_SEGN_BITS=3 +#default CONFIG_PCI_BUS_SEGN_BITS=3 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 -default DCACHE_RAM_BASE=0xc4000 -default DCACHE_RAM_SIZE=0x0c000 -#default DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 +default CONFIG_USE_DCACHE_RAM=1 +default CONFIG_DCACHE_RAM_BASE=0xc4000 +default CONFIG_DCACHE_RAM_SIZE=0x0c000 +#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000 +default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000 default CONFIG_USE_INIT=0 #default CONFIG_AP_CODE_IN_CAR=1 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 +default CONFIG_MEM_TRAIN_SEQ=2 +default CONFIG_WAIT_BEFORE_CPUS_INIT=0 default CONFIG_AMDMCT = 1 @@ -253,10 +253,10 @@ default CONFIG_IOAPIC=1 ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="Cheetah Fam10" -default MAINBOARD_VENDOR="AMD" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10" +default CONFIG_MAINBOARD_VENDOR="AMD" +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 +default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## ## Set microcode patch file name @@ -266,34 +266,34 @@ default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h" ## Shanghai rev DA-C2: "mc_patch_0100009f.h" ## -default AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" +default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h" ### ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 768k heap ## -default HEAP_SIZE=0xc0000 +default CONFIG_HEAP_SIZE=0xc0000 ## ## Only use the option table in a normal image ## -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) +default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE ) ## ## Coreboot C code runs at this location in RAM ## -default _RAMBASE=0x00200000 +default CONFIG_RAMBASE=0x00200000 ## ## Load the payload from the ROM @@ -307,8 +307,8 @@ default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## Disable the gdb stub by default @@ -325,21 +325,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1 default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 +default CONFIG_TTYS0_BAUD=115200 +#default CONFIG_TTYS0_BAUD=57600 +#default CONFIG_TTYS0_BAUD=38400 +#default CONFIG_TTYS0_BAUD=19200 +#default CONFIG_TTYS0_BAUD=9600 +#default CONFIG_TTYS0_BAUD=4800 +#default CONFIG_TTYS0_BAUD=2400 +#default CONFIG_TTYS0_BAUD=1200 # Select the serial console base port -default TTYS0_BASE=0x3f8 +default CONFIG_TTYS0_BASE=0x3f8 # Select the serial protocol # This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 +default CONFIG_TTYS0_LCS=0x3 ## ### Select the coreboot loglevel @@ -351,17 +351,17 @@ default TTYS0_LCS=0x3 ## WARNING 5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## DEBUG 8 debug-level messages +## CONFIG_DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 ## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 ## ## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" ### End Options.lb # diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index ed53938a63..8239a115bf 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -49,7 +49,7 @@ static void dump_mem(u32 start, u32 end) extern u8 AmlCode[]; extern u8 AmlCode_ssdt[]; -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 extern u8 AmlCode_ssdt2[]; extern u8 AmlCode_ssdt3[]; extern u8 AmlCode_ssdt4[]; @@ -276,7 +276,7 @@ unsigned long write_acpi_tables(unsigned long start) printk_debug("ACPI: * SSDT for PState at %lx\n", current); current = acpi_add_ssdt_pstates(rsdt, current); -#if ACPI_SSDTX_NUM >= 1 +#if CONFIG_ACPI_SSDTX_NUM >= 1 /* same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index 49dadd799a..fbb8c14388 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -50,9 +50,9 @@ #include "lib/delay.c" #if NODE_NUMS == 64 - #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CBB,CDB+x,fn):PCI_DEV(CBB-1, CDB+x-32, fn)) + #define NODE_PCI(x,fn) ((x<32)?PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn):PCI_DEV(CONFIG_CBB-1, CONFIG_CDB+x-32, fn)) #else - #define NODE_PCI(x, fn) PCI_DEV(CBB,CDB+x,fn) + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,CONFIG_CDB+x,fn) #endif //#include "cpu/x86/lapic/boot_cpu.c" @@ -73,8 +73,8 @@ void hardwaremain(int ret_addr) { - struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c index 38196b262e..4e484553f7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -60,7 +60,7 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "arch/i386/lib/console.c" #include "pc80/serial.c" #include "ram/ramtest.c" @@ -80,7 +80,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #include "cpu/x86/bist.h" -#if (USE_FAILOVER_IMAGE == 0) +#if (CONFIG_USE_FAILOVER_IMAGE == 0) #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -142,10 +142,10 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" -#endif /* (USE_FAILOVER_IMAGE == 0) */ +#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */ -#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) +#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -190,7 +190,7 @@ normal_image: ); fallback_image: - #if HAVE_FAILOVER_BOOT==1 + #if CONFIG_HAVE_FAILOVER_BOOT==1 __asm__ volatile ("jmp __fallback_image" : /* outputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ @@ -198,22 +198,22 @@ fallback_image: #endif ; } -#endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) */ +#endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) */ void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a USE_FAILOVER_IMAGE=0. -#if HAVE_FAILOVER_BOOT==1 - #if USE_FAILOVER_IMAGE==1 +//FIXME: I think that there is a hole here with the real_main() logic realmain is inside a CONFIG_USE_FAILOVER_IMAGE=0. +#if CONFIG_HAVE_FAILOVER_BOOT==1 + #if CONFIG_USE_FAILOVER_IMAGE==1 failover_process(bist, cpu_init_detectedx); #else real_main(bist, cpu_init_detectedx); #endif #else - #if USE_FALLBACK_IMAGE == 1 + #if CONFIG_USE_FALLBACK_IMAGE == 1 failover_process(bist, cpu_init_detectedx); #endif real_main(bist, cpu_init_detectedx); @@ -221,7 +221,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#if (USE_FAILOVER_IMAGE==0) +#if (CONFIG_USE_FAILOVER_IMAGE==0) #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -229,7 +229,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; msr_t msr; @@ -243,12 +243,12 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk_debug("\n"); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -380,4 +380,4 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) } -#endif /* USE_FAILOVER_IMAGE==0 */ +#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */ diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c index d1d1ff8e32..de8eacde6b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/irq_tables.c @@ -116,11 +116,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) } -#if CBB - write_pirq_info(pirq_info, CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +#if CONFIG_CBB + write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; if(sysconf.nodes>32) { - write_pirq_info(pirq_info, CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; } #endif diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 04698d7369..25093fd8b1 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40 bit address * that define the end of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40-bit address * that define the start of the DRAM region. */ -// PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR_FAM10 - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -128,14 +128,14 @@ static void setup_mb_resource_map(void) * This field defines the upp adddress bits of a 40-bit address that * defines the end of a memory-mapped I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -163,14 +163,14 @@ static void setup_mb_resource_map(void) * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -197,10 +197,10 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -227,10 +227,10 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -268,10 +268,10 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration regin i */ -// PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 - PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; int max; |