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authorStefan Reinauer <stepan@openbios.org>2004-01-21 16:05:40 +0000
committerStefan Reinauer <stepan@openbios.org>2004-01-21 16:05:40 +0000
commitbd4be244bb0aa951f15dda2246a83f6da5734b55 (patch)
treee6b1ab3faa4428928bab37751b218bcd0dfac724 /src/mainboard/amd/solo/Config.lb
parentb020d53352c1bbe1084c9c499b45cfb345fc8677 (diff)
downloadcoreboot-bd4be244bb0aa951f15dda2246a83f6da5734b55.tar.xz
update mp table and pirq table
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/solo/Config.lb')
-rw-r--r--src/mainboard/amd/solo/Config.lb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/solo/Config.lb b/src/mainboard/amd/solo/Config.lb
index 1f6b988d01..1372e46005 100644
--- a/src/mainboard/amd/solo/Config.lb
+++ b/src/mainboard/amd/solo/Config.lb
@@ -45,7 +45,7 @@ default HAVE_HARD_RESET=1
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=7
+default IRQ_SLOT_COUNT=8
##
## Build code to export an x86 MP table
@@ -252,7 +252,7 @@ northbridge amd/amdk8 "mc0"
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
- pci 1:1.0 on
+ # pci 1:1.0 off
superio NSC/pc87360 link 1
pnp 2e.0
pnp 2e.1