diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2003-04-24 06:57:32 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-04-24 06:57:32 +0000 |
| commit | 497eb854415a0e54609fc747321c75b81c7df7c6 (patch) | |
| tree | 19bed1099b83496e5c6dab543eb2290192c414ba /src/mainboard/amd/solo | |
| parent | 8cd55d7f4a90d8c1499dddd319db12e6c4942e51 (diff) | |
| download | coreboot-497eb854415a0e54609fc747321c75b81c7df7c6.tar.xz | |
- irq routing table generated by getpir
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd/solo')
| -rw-r--r-- | src/mainboard/amd/solo/irq_tables.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/amd/solo/irq_tables.c b/src/mainboard/amd/solo/irq_tables.c new file mode 100644 index 0000000000..613cc1e111 --- /dev/null +++ b/src/mainboard/amd/solo/irq_tables.c @@ -0,0 +1,31 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*7, /* there can be total 7 devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x38, /* Where the interrupt router lies (dev) */ + 0xc20, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x7468, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x39, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {0x2,0x28, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0}, + {0x2,0x30, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0x3, 0}, + {0x2,0x38, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x4, 0}, + {0x2,0x8, {{0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}, {0x1, 0xdeb8}}, 0, 0}, + {0,0x39, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, + {0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0}, + {0xff,0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff}, + } +}; |