AMD South Station: Use SPD read code from F14 wrapper

Changes:
 - Get rid of the south_station mainboard specific code and
   use the platform generic function wrapper that was added
   in change http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2608
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 7 insertions, 0 deletions

diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb
index 883166ce9c..60335d75d2 100644
--- a/src/mainboard/amd/south_station/devicetree.cb
+++ b/src/mainboard/amd/south_station/devicetree.cb
@@ -99,6 +99,13 @@ chip northbridge/amd/agesa/family14/root_complex
                         device pci 18.3 on end
                         device pci 18.4 on end
                         device pci 18.5 on end
+
+                        register "spdAddrLookup" = "
+                        {
+                            { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+                            { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+                        }"
+
                 end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
         end #domain
 end #northbridge/amd/agesa/family14/root_complex