diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 08:03:49 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:47:18 +0100 |
| commit | 7d25651ed3eb78228a00b479454d0ab2417f3f2a (patch) | |
| tree | 07c33833b4a763def10d3c7002439a04c1468f76 /src/mainboard/amd/south_station | |
| parent | 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 (diff) | |
| download | coreboot-7d25651ed3eb78228a00b479454d0ab2417f3f2a.tar.xz | |
AGESA f14: Consolidate early P-states setting
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/amd/south_station')
| -rw-r--r-- | src/mainboard/amd/south_station/romstage.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5ef95a0ceb..4b725c07ab 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { |