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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-23 14:27:44 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-24 05:34:13 +0200 |
| commit | 9d035fa1f7021fda52cd56aede406de7b780dfa8 (patch) | |
| tree | facbfcbbfbf835d737a6ef90128facfff2457f89 /src/mainboard/amd/south_station | |
| parent | 7fb149dce1d13be7dfae8ec1babb000ef18d2d94 (diff) | |
| download | coreboot-9d035fa1f7021fda52cd56aede406de7b780dfa8.tar.xz | |
AGESA binaryPI boards: Drop annoying commentary
Same comments were already removed for the latest board, the amd/lamar.
Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10283
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Diffstat (limited to 'src/mainboard/amd/south_station')
| -rw-r--r-- | src/mainboard/amd/south_station/PlatformGnbPcie.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index b36489d8d1..e94b49bf46 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -53,20 +53,20 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) }, #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) }, @@ -79,7 +79,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) } |