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| author | John Zhao <john.zhao@intel.com> | 2020-05-13 16:27:03 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-06-02 20:14:44 +0000 |
| commit | b1c53fc94a05ace5316395cb528567fc92747495 (patch) | |
| tree | dfa6ea90909636c249582ccfc04d2a6f2c3d4b30 /src/mainboard/amd/south_station | |
| parent | 695d86243e7d2291b670d12b61446bd50708377e (diff) | |
| download | coreboot-b1c53fc94a05ace5316395cb528567fc92747495.tar.xz | |
mb/intel/tglrvp: Enable TCSS xHCI, PCIe root ports and DMA controllers
This explicitly enables TCSS xHCI, PCIe root ports and DMA controllers
from TGL RVP platform devicetree setting.
BUG=:b:146624360
TEST=Built and booted on TGL RVP.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0111542eef253f469f679cdc4b81812438dff4ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/amd/south_station')
0 files changed, 0 insertions, 0 deletions