diff options
| author | Martin Roth <martin@se-eng.com> | 2013-01-10 12:41:40 -0700 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2013-01-21 18:52:30 +0100 |
| commit | 2d8815197e7a8f7fa8c7e7dd6127937093369c7c (patch) | |
| tree | 4730703aa9a4c523f59f31f5f710c929b0a74480 /src/mainboard/amd/thatcher/devicetree.cb | |
| parent | b867281a07addd1eb00f964ff4f8727664e13e19 (diff) | |
| download | coreboot-2d8815197e7a8f7fa8c7e7dd6127937093369c7c.tar.xz | |
F15tn: Modify devicetree to fix S3 resume
The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.
There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link. These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.
The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.
Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/thatcher/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/thatcher/devicetree.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 2a91e1a5d5..561a5b2a4e 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -25,7 +25,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci_domain 0 on subsystemid 0x1022 0x1410 inherit chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device pci 18.0 on # northbridge chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 @@ -38,7 +37,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 7.0 on end # LAN device pci 8.0 off end # NB/SB Link P2P bridge end - end chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 10.1 on end # XHCI HC1 @@ -92,7 +90,7 @@ chip northbridge/amd/agesa/family15tn/root_complex register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "gpp_configuration" = "4" end #southbridge/amd/hudson -# device pci 18.0 on end + device pci 18.0 on end #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end |