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authorMartin Roth <martin.roth@se-eng.com>2013-01-16 19:18:09 -0700
committerMartin Roth <martin.roth@se-eng.com>2013-01-21 18:53:11 +0100
commitc89d3daf32476f02b0bea7dc84572adfad55fc3d (patch)
tree68e212131f096e7d4ca59b41900efe7b35e8724f /src/mainboard/amd/thatcher/devicetree.cb
parent2d8815197e7a8f7fa8c7e7dd6127937093369c7c (diff)
downloadcoreboot-c89d3daf32476f02b0bea7dc84572adfad55fc3d.tar.xz
Parmer / Thatcher: devicetree.cb cleanup and whitespace
Re-formatting and cleaning up the devicetree.cb files for parmer and thatcher. Change-Id: Ic458e59701c1f2593b0a035b96cac60df476ee82 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2164 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Diffstat (limited to 'src/mainboard/amd/thatcher/devicetree.cb')
-rw-r--r--src/mainboard/amd/thatcher/devicetree.cb163
1 files changed, 83 insertions, 80 deletions
diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb
index 561a5b2a4e..f6459c152f 100644
--- a/src/mainboard/amd/thatcher/devicetree.cb
+++ b/src/mainboard/amd/thatcher/devicetree.cb
@@ -17,86 +17,89 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
chip northbridge/amd/agesa/family15tn/root_complex
- device lapic_cluster 0 on
- chip cpu/amd/agesa/family15tn
- device lapic 10 on end
- end
- end
- device pci_domain 0 on
- subsystemid 0x1022 0x1410 inherit
- chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
- chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
- device pci 0.0 on end # Root Complex
- device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
- device pci 1.1 on end # Internal Multimedia
- device pci 2.0 on end # PCIE SLOT0 x16
- device pci 3.0 on end # PCIE SLOT0 x16
- device pci 4.0 on end # PCIE MINI0
- device pci 5.0 on end # PCIE MINI1
- device pci 6.0 on end # PCIE Slot1 x1
- device pci 7.0 on end # LAN
- device pci 8.0 off end # NB/SB Link P2P bridge
- end
- chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
- device pci 10.0 on end # XHCI HC0
- device pci 10.1 on end # XHCI HC1
- device pci 11.0 on end # SATA
- device pci 12.0 on end # USB
- device pci 12.2 on end # USB
- device pci 13.0 on end # USB
- device pci 13.2 on end # USB
- device pci 14.0 on # SM
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
+
+ device lapic_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device pci_domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIE SLOT0 x16
+ device pci 3.0 on end # PCIE SLOT0 x16
+ device pci 4.0 on end # PCIE MINI0
+ device pci 5.0 on end # PCIE MINI1
+ device pci 6.0 on end # PCIE Slot1 x1
+ device pci 7.0 on end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/smsc/lpc47n217
+ device pnp 2e.3 off # Parallel
+ io 0x60 = 0x378
+ irq 0x70 = 7
end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
end
- end # SM
- device pci 14.1 on end # IDE 0x439c
- device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/smsc/lpc47n217
- device pnp 2e.3 off # Parallel
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- end #superio/smsc/lpc47n217
- end
- device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
- device pci 14.5 on end # USB 2
-# device pci 14.6 on end # Gec
- device pci 14.7 on end
- device pci 15.0 off end # PCIe 0
- device pci 15.1 off end # PCIe 1
- device pci 15.2 off end # PCIe 2
- device pci 15.3 off end # PCIe 3
-# device pci 16.0 off end # XHCI0 Hudson2 only
-# device pci 16.2 off end # XHCI1 Hudson2 only
- register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- register "gpp_configuration" = "4"
- end #southbridge/amd/hudson
- device pci 18.0 on end
- #device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 18.5 on end
- end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
- end #pci_domain
-end #northbridge/amd/agesa/family15tn/root_complex
+ end #chip superio/smsc/lpc47n217
+ end #device pci 14.3 # LPC
+ device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
+ device pci 14.5 on end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 on end # SD
+ device pci 15.0 off end # PCIe 0
+ device pci 15.1 off end # PCIe 1
+ device pci 15.2 off end # PCIe 2
+ device pci 15.3 off end # PCIe 3
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ register "gpp_configuration" = "4"
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #pci_domain
+end #chip northbridge/amd/agesa/family15tn/root_complex