summaryrefslogtreecommitdiff
path: root/src/mainboard/amd/thatcher/mainboard.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-27 13:32:59 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-03 09:50:41 +0200
commit6a089e3b18ebb5561ae7233d28ff53fff9fbe676 (patch)
treecb85377196643223de2d8977d32ccd6c1e4c0868 /src/mainboard/amd/thatcher/mainboard.c
parentdb8693bde7ad2cc2f6b32bb9654685c1ddb502b2 (diff)
downloadcoreboot-6a089e3b18ebb5561ae7233d28ff53fff9fbe676.tar.xz
AGESA boards: Use acpi_is_wakeup_s3()
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/amd/thatcher/mainboard.c')
-rw-r--r--src/mainboard/amd/thatcher/mainboard.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c
index bfb664f4b3..2eacf76ef8 100644
--- a/src/mainboard/amd/thatcher/mainboard.c
+++ b/src/mainboard/amd/thatcher/mainboard.c
@@ -51,16 +51,8 @@ static void mainboard_enable(device_t dev)
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
- /*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the appropriate AGESA/CIMx resume functions.
- */
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = acpi_get_sleep_type();
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
-
-#endif
}
struct chip_operations mainboard_ops = {