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| author | Martin Roth <martin.roth@se-eng.com> | 2013-01-18 12:55:40 -0700 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2013-01-21 18:55:33 +0100 |
| commit | f5726ea544af904061b754fb6e369e477e93f0a5 (patch) | |
| tree | d6a551008e87cff5ad02f3ea567e2f3a79a40674 /src/mainboard/amd/thatcher/mptable.c | |
| parent | 2892023fd422794bb82658dde3e8d489af2bdd55 (diff) | |
| download | coreboot-f5726ea544af904061b754fb6e369e477e93f0a5.tar.xz | |
Hudson: Cleanup - change SB800 references to hudson
Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.
This is just cleanup and should make no functional difference.
Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/mainboard/amd/thatcher/mptable.c')
| -rw-r--r-- | src/mainboard/amd/thatcher/mptable.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 329f731f2e..4cdea62b9f 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -30,11 +30,11 @@ //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS -extern u8 bus_sb800[3]; +extern u8 bus_hudson[3]; extern u32 bus_type[256]; -extern u32 sbdn_sb800; -extern u32 apicid_sb800; +extern u32 sbdn_hudson; +extern u32 apicid_hudson; u8 picr_data[] = { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, @@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v) /* Set IO APIC ID onto IO_APIC_ID */ write32 (dword, 0x00); write32 (dword + 0x10, IO_APIC_ID << 24); - apicid_sb800 = IO_APIC_ID; - smp_write_ioapic(mc, apicid_sb800, 0x21, dword); + apicid_hudson = IO_APIC_ID; + smp_write_ioapic(mc, apicid_hudson, 0x21, dword); /* PIC IRQ routine */ for (byte = 0x0; byte < sizeof(picr_data); byte ++) { @@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v) /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v) /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); + PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14); + PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15); + PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16); + PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); + PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15); + PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16); + PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17); + PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); - - PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); - PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); - PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16); + PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17); + PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14); + PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15); + + PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12); + PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13); + PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14); /* PCIe Lan*/ PCI_INT(0x0, 0x06, 0x0, 0x13); |