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authorZheng Bao <fishbaozi@gmail.com>2013-01-05 12:17:46 +0800
committerMarc Jones <marcj303@gmail.com>2013-01-11 00:42:07 +0100
commit105da50df4fe6073575a2eb6247d916746b6143e (patch)
treea7c23555a675299e2ecd691abbc7d57ca1e7f80c /src/mainboard/amd/thatcher
parent8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a (diff)
downloadcoreboot-105da50df4fe6073575a2eb6247d916746b6143e.tar.xz
AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. The supermicro/h8scm needs more work. Currently it is set as it was. We need to check if the F10 and F15 have different value. Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1661 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/amd/thatcher')
-rw-r--r--src/mainboard/amd/thatcher/agesawrapper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index 67ac8e9e53..7a3616b480 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -166,7 +166,7 @@ agesawrapper_amdinitmmio (
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
- MsrReg = (0x1000000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+ MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;