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| author | Stefan Reinauer <reinauer@chromium.org> | 2013-05-09 16:30:06 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 02:40:30 +0200 |
| commit | 6adef0847e4a62abf00e489209d239c958447830 (patch) | |
| tree | 5e6cbc1a6f84cca69b7060710b73b1d31c00ccf5 /src/mainboard/amd/thatcher | |
| parent | 2ae6d6f6de3d5fb6c1fdb039d0997814ac0b9798 (diff) | |
| download | coreboot-6adef0847e4a62abf00e489209d239c958447830.tar.xz | |
Rename hardwaremain() to main()
... and drop the wrapper on ARMv7
Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3639
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/thatcher')
| -rw-r--r-- | src/mainboard/amd/thatcher/get_bus_conf.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index 3ae4c18195..d1be8b6268 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) * call. The logically correct place to call AmdInitLate is after PCI scan is done, * after the decision about S3 resume is made, and before the system tables are * written into RAM. The routine that is responsible for writing the tables is - * "write_tables", called near the end of "hardwaremain". There is no platform + * "write_tables", called near the end of "main". There is no platform * specific entry point between the S3 resume decision point and the call to * "write_tables", and the next platform specific entry points are the calls to * the ACPI table write functions. The first of ose would seem to be the right |