Hudson: Cleanup - change SB800 references to hudson

Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.

This is just cleanup and should make no functional difference.

Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>

7 files changed, 46 insertions, 49 deletions

diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c
index 0a64535e00..0cdea2dc12 100644
--- a/src/mainboard/amd/thatcher/acpi_tables.c
+++ b/src/mainboard/amd/thatcher/acpi_tables.c
@@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
 
-	/* Write SB800 IOAPIC, only one */
+	/* Write Hudson IOAPIC, only one */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
 					   IO_APIC_ADDR, 0);
 
diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c
index aaff34b2ca..7b002b4c9b 100644
--- a/src/mainboard/amd/thatcher/agesawrapper.c
+++ b/src/mainboard/amd/thatcher/agesawrapper.c
@@ -100,7 +100,7 @@ agesawrapper_amdinitcpuio (
 	PciData = 1;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
 	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 	 * set to non-posted regions.
 	 */
diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl
index e0cc3fd54e..4b600e84e0 100644
--- a/src/mainboard/amd/thatcher/dsdt.asl
+++ b/src/mainboard/amd/thatcher/dsdt.asl
@@ -188,7 +188,7 @@ DefinitionBlock (
 		PM2D, 0x00000008,
 	}
 
-	/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+	/* Power Management I/O registers. */
 	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
 		Field(PIOR, ByteAcc, NoLock, Preserve) {
 		PIOI, 0x00000008,
diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c
index 2636b9e49a..47b4f74626 100644
--- a/src/mainboard/amd/thatcher/get_bus_conf.c
+++ b/src/mainboard/amd/thatcher/get_bus_conf.c
@@ -30,8 +30,8 @@
  * and acpi_tables busnum is default.
  */
 u8 bus_isa;
-u8 bus_sb800[3];
-u32 apicid_sb800;
+u8 bus_hudson[3];
+u32 apicid_hudson;
 
 /*
  * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@@ -43,7 +43,7 @@ u32 pci1234x[] = {
 };
 
 u32 bus_type[256];
-u32 sbdn_sb800;
+u32 sbdn_hudson;
 
 static u32 get_bus_conf_done = 0;
 
@@ -95,10 +95,10 @@ void get_bus_conf(void)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
 #endif
 
-	sbdn_sb800 = 0;
+	sbdn_hudson = 0;
 
 	for (i = 0; i < 3; i++) {
-		bus_sb800[i] = 0;
+		bus_hudson[i] = 0;
 	}
 
 	for (i = 0; i < 256; i++) {
@@ -107,34 +107,33 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;  /* pci */
 
-	//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-	bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+	bus_hudson[0] = (pci1234x[0] >> 16) & 0xff;
 
-	/* sb800 */
-	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+	/* Hudson */
+	dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4));
 
 	if (dev) {
-		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
 		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_isa++;
-		for (j = bus_sb800[1]; j < bus_isa; j++)
+		for (j = bus_hudson[1]; j < bus_isa; j++)
 			bus_type[j] = 1;
 	}
 
 	for (i = 0; i < 4; i++) {
-		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+		dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i));
 		if (dev) {
-			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 			bus_isa++;
 		}
 	}
-	for (j = bus_sb800[2]; j < bus_isa; j++)
+	for (j = bus_hudson[2]; j < bus_isa; j++)
 		bus_type[j] = 1;
 
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
 	apicid_base = CONFIG_MAX_CPUS;
-	apicid_sb800 = apicid_base;
+	apicid_hudson = apicid_base;
 }
diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c
index 3bcd3fb89a..3eb036a207 100644
--- a/src/mainboard/amd/thatcher/irq_tables.c
+++ b/src/mainboard/amd/thatcher/irq_tables.c
@@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
 }
 
 extern u8 bus_isa;
-extern u8 bus_sb800[2];
-extern unsigned long sbdn_sb800;
+extern u8 bus_hudson[2];
+extern unsigned long sbdn_hudson;
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
@@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;
 
-	pirq->rtr_bus = bus_sb800[0];
-	pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+	pirq->rtr_bus = bus_hudson[0];
+	pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4;
 
 	pirq->exclusive_irqs = 0;
 
@@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	slot_num = 0;
 
 	/* pci bridge */
-	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+	write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4,
 			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
 			0);
 	pirq_info++;
diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c
index 329f731f2e..4cdea62b9f 100644
--- a/src/mainboard/amd/thatcher/mptable.c
+++ b/src/mainboard/amd/thatcher/mptable.c
@@ -30,11 +30,11 @@
 
 //-#define IO_APIC_ID    CONFIG_MAX_PHYSICAL_CPUS + 1
 #define IO_APIC_ID    CONFIG_MAX_CPUS
-extern u8 bus_sb800[3];
+extern u8 bus_hudson[3];
 
 extern u32 bus_type[256];
-extern u32 sbdn_sb800;
-extern u32 apicid_sb800;
+extern u32 sbdn_hudson;
+extern u32 apicid_hudson;
 
 u8 picr_data[] = {
 	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v)
 	/* Set IO APIC ID onto IO_APIC_ID */
 	write32 (dword, 0x00);
 	write32 (dword + 0x10, IO_APIC_ID << 24);
-	apicid_sb800 = IO_APIC_ID;
-	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+	apicid_hudson = IO_APIC_ID;
+	smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
 
 	/* PIC IRQ routine */
 	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v)
 	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
 	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
 
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
 #define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
 
 	/* Internal VGA */
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
@@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v)
 
 	/* PCI slots */
 	/* PCI_SLOT 0. */
-	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+	PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
 
 	/* PCI_SLOT 1. */
-	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+	PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
 
 	/* PCI_SLOT 2. */
-	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
+
+	PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
+	PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
+	PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
 
 	/* PCIe Lan*/
 	PCI_INT(0x0, 0x06, 0x0, 0x13);
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 445fe45e72..1c9ab10f3f 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -85,14 +85,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if(val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
 
 	val = agesawrapper_amdinitearly ();