diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-01 15:10:11 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-10-04 14:30:04 +0200 |
commit | 5c22825c1924b1f5fb9cebff8e13b83792d3ecb9 (patch) | |
tree | d7849719b4b155555d381e68a2bf6a587e21ae47 /src/mainboard/amd/torpedo/OemCustomize.c | |
parent | 738a3b043e92bf3036f4f9131ecc3d636016ffa7 (diff) | |
download | coreboot-5c22825c1924b1f5fb9cebff8e13b83792d3ecb9.tar.xz |
mainboard/amd/torpedo: Improve code formatting
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/torpedo/OemCustomize.c')
-rw-r--r-- | src/mainboard/amd/torpedo/OemCustomize.c | 196 |
1 files changed, 98 insertions, 98 deletions
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 2293039c25..3c20047a31 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -23,70 +23,70 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) - }, - // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) - }, - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) - } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } + // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) + }, + // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) + }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) +// { +// DESCRIPTOR_TERMINATE_LIST, +// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), +// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) +// } }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) - }, - // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) - } + // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) + } }; static const PCIe_COMPLEX_DESCRIPTOR Llano = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] }; /*---------------------------------------------------------------------------------------*/ @@ -107,58 +107,58 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = { static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) { - AGESA_STATUS Status; - VOID *LlanoPcieComplexListPtr; - VOID *LlanoPciePortPtr; - VOID *LlanoPcieDdiPtr; + AGESA_STATUS Status; + VOID *LlanoPcieComplexListPtr; + VOID *LlanoPciePortPtr; + VOID *LlanoPcieDdiPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; - // GNB PCIe topology Porting + // GNB PCIe topology Porting - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList); - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); ASSERT(Status == AGESA_SUCCESS); - LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof(Llano); - LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof(Llano); + LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - AllocHeapParams.BufferPtr += sizeof(PortList); - LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof(PortList); + LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill (LlanoPcieComplexListPtr, - 0, - sizeof(Llano), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPcieComplexListPtr, + 0, + sizeof(Llano), + &InitEarly->StdHeader); - LibAmdMemFill (LlanoPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPciePortPtr, + 0, + sizeof(PortList), + &InitEarly->StdHeader); - LibAmdMemFill (LlanoPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + LibAmdMemFill (LlanoPcieDdiPtr, + 0, + sizeof(DdiList), + &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); - ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr; - InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; return AGESA_SUCCESS; } @@ -174,9 +174,9 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), - PSO_END + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + PSO_END }; const struct OEM_HOOK OemCustomize = { |