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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-23 15:40:08 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-26 08:35:43 +0000 |
commit | e1dced4561ed3b7bff98984c1d51b8e84f004b47 (patch) | |
tree | 8e52e9059cedb2a9608c472480950e5463f61bc4 /src/mainboard/amd/torpedo/OemCustomize.c | |
parent | b6850ddbffa216ae7306d612fafb460ef1608d6f (diff) | |
download | coreboot-e1dced4561ed3b7bff98984c1d51b8e84f004b47.tar.xz |
amd/torpedo: Drop PlatformGnbPcieComplex.h
Copy-paste, was not really used at all.
Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/amd/torpedo/OemCustomize.c')
-rw-r--r-- | src/mainboard/amd/torpedo/OemCustomize.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 196e8bbaa4..e5a3159cbe 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include "PlatformGnbPcieComplex.h" #include <string.h> #include <northbridge/amd/agesa/state_machine.h> @@ -59,12 +58,6 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { |