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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-01 15:10:11 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-10-04 14:30:04 +0200 |
| commit | 5c22825c1924b1f5fb9cebff8e13b83792d3ecb9 (patch) | |
| tree | d7849719b4b155555d381e68a2bf6a587e21ae47 /src/mainboard/amd/torpedo/buildOpts.c | |
| parent | 738a3b043e92bf3036f4f9131ecc3d636016ffa7 (diff) | |
| download | coreboot-5c22825c1924b1f5fb9cebff8e13b83792d3ecb9.tar.xz | |
mainboard/amd/torpedo: Improve code formatting
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/torpedo/buildOpts.c')
| -rw-r--r-- | src/mainboard/amd/torpedo/buildOpts.c | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index d81748af92..656102d015 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -96,17 +96,19 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + // This is the delivery package title, "LlanoPI " + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '} -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. +/* The following definitions specify the default values for various parameters + * in which there are no clearly defined defaults to be used in the common file. + * The values below are based on product and BKDG content, please consult the + * AGESA Memory team for consultation. + */ #define DFLT_SCRUB_DRAM_RATE (0) #define DFLT_SCRUB_L2_RATE (0) #define DFLT_SCRUB_L3_RATE (0) @@ -185,18 +187,18 @@ */ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = { - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, - { CPU_LIST_TERMINAL } + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull }, + { CPU_LIST_TERMINAL } }; #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList |