src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 68 insertions, 68 deletions

diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb
index 2ce1dfd29e..2adfb27274 100644
--- a/src/mainboard/amd/torpedo/devicetree.cb
+++ b/src/mainboard/amd/torpedo/devicetree.cb
@@ -13,56 +13,56 @@
 # GNU General Public License for more details.
 #
 chip northbridge/amd/agesa/family12/root_complex
-        device cpu_cluster 0 on
-                chip cpu/amd/agesa/family12
-                  device lapic 0 on end
-                end
-        end
-        device domain 0 on
-                subsystemid 0x1022 0x1705 inherit
-                chip northbridge/amd/agesa/family12 # CPU side of HT root complex
-                                chip northbridge/amd/agesa/family12 # PCI side of HT root complex
-                                        device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics Bridge
-                                        device pci 1.1 on end # Audio Controller
-                                        device pci 2.0 on end # Root Port
-                                        device pci 3.0 on end # Root Port
-                                        device pci 4.0 on end # PCIE P2P bridge
-                                        device pci 5.0 on end # PCIE P2P bridge
-                                        device pci 6.0 on end # PCIE P2P bridge
-                                        device pci 7.0 on end # PCIE P2P bridge
-                                        device pci 8.0 on end # NB/SB Link P2P bridge
-                                end # agesa northbridge
-                                chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
-                                        device pci 10.0 on end # USB XHCI
-                                        device pci 10.1 on end # USB XHCI
-                                        device pci 11.0 on end # SATA
-                                        device pci 12.0 on end # USB
-                                        device pci 12.2 on end # USB
-                                        device pci 13.0 on end # USB
-                                        device pci 13.2 on end # USB
-                                        device pci 14.0 on # SM
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end
-                                        end # SM
-                                        device pci 14.1 on end # IDE
-                                        device pci 14.2 on end # HDA
-                                        device pci 14.3 on # LPC
-												chip superio/smsc/kbc1100
-                                                        device pnp 2e.7 on #  Keyboard
-                                                                io 0x60 = 0x60
-                                                                io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                                irq 0x72 = 12
-                                                        end
-                                                end # kbc1100
-										end #LPC
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family12
+			device lapic 0 on end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x1022 0x1705 inherit
+		chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+				chip northbridge/amd/agesa/family12 # PCI side of HT root complex
+					device pci 0.0 on end # Root Complex
+					device pci 1.0 on end # Internal Graphics Bridge
+					device pci 1.1 on end # Audio Controller
+					device pci 2.0 on end # Root Port
+					device pci 3.0 on end # Root Port
+					device pci 4.0 on end # PCIE P2P bridge
+					device pci 5.0 on end # PCIE P2P bridge
+					device pci 6.0 on end # PCIE P2P bridge
+					device pci 7.0 on end # PCIE P2P bridge
+					device pci 8.0 on end # NB/SB Link P2P bridge
+				end # agesa northbridge
+				chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus
+					device pci 10.0 on end # USB XHCI
+					device pci 10.1 on end # USB XHCI
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.2 on end # USB
+					device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE
+					device pci 14.2 on end # HDA
+					device pci 14.3 on # LPC
+						chip superio/smsc/kbc1100
+							device pnp 2e.7 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+						end # kbc1100
+					end #LPC
 					device pci 14.4 on end # PCI bridge
-	  				device pci 14.5 on end # USB 2
+					device pci 14.5 on end # USB 2
 					device pci 14.6 on end # Ethernet Controller
 					device pci 14.7 on end # SD Flash Controller
 					device pci 15.0 on end # PCIe PortA
@@ -70,16 +70,16 @@ chip northbridge/amd/agesa/family12/root_complex
 					device pci 15.2 on end # PCIe PortC
 					device pci 15.3 on end # PCIe PortD
 					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb900
-                        device pci 18.0 on end
-                        device pci 18.1 on end
-                        device pci 18.2 on end
-                        device pci 18.3 on end
-                        device pci 18.4 on end
-                        device pci 18.5 on end
-                        device pci 18.6 on end
-                        device pci 18.7 on end
-                end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
-        end #domain
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+		end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex
+	end #domain
 end #northbridge/amd/agesa/family12/root_complex
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl
index 0c55ff4c1b..4ee5fb4ad7 100644
--- a/src/mainboard/amd/torpedo/dsdt.asl
+++ b/src/mainboard/amd/torpedo/dsdt.asl
@@ -676,7 +676,7 @@ DefinitionBlock (
 
 		/* On older chips, clear PciExpWakeDisEn */
 		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*    	Store(0,\_SB.PWDE)
+		*	Store(0,\_SB.PWDE)
 		*}
 		*/
 
@@ -691,13 +691,13 @@ DefinitionBlock (
 	*  used, so it could be removed.
 	*
 	*
-	*  	\_GTS OEM Going To Sleep method
+	*	\_GTS OEM Going To Sleep method
 	*
-	*  	Entry:
-	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
 	*
-	*  	Exit:
-	*  		-none-
+	*	Exit:
+	*		-none-
 	*
 	*  Method(\_GTS, 1) {
 	*  DBGO("\\_GTS\n")
@@ -766,7 +766,7 @@ DefinitionBlock (
 	} /* End Method(\_WAK) */
 
 	Scope(\_GPE) {	/* Start Scope GPE */
-	} 	/* End Scope GPE */
+	}	/* End Scope GPE */
 
 	/* System Bus */
 	Scope(\_SB) { /* Start \_SB scope */
diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c
index 5a77dc0de0..e26052a734 100644
--- a/src/mainboard/amd/torpedo/gpio.c
+++ b/src/mainboard/amd/torpedo/gpio.c
@@ -75,7 +75,7 @@ void gpioEarlyInit(void) {
 	StripInfo = (Data8 & BIT7) >> 7;
 	Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
 	StripInfo |= (Data8 & BIT7) >> 6;
-	if (StripInfo < boardRevC) { 		// for old board. Rev B
+	if (StripInfo < boardRevC) {		// for old board. Rev B
 		Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);		// function 3
 		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0
 	}