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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-24 08:53:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-09-26 13:38:46 +0200
commitb87a734771449ed06cd91621da4c893a1ad722b0 (patch)
tree9ca49309fba09071aeaab4cecc9e80ed94ca9a0e /src/mainboard/amd/torpedo
parent8da96e57c89860f429f1bf590c10fa364b8019d4 (diff)
downloadcoreboot-b87a734771449ed06cd91621da4c893a1ad722b0.tar.xz
mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/amd/torpedo')
-rw-r--r--src/mainboard/amd/torpedo/dsdt.asl14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl
index 2014a91f42..f257f23ec1 100644
--- a/src/mainboard/amd/torpedo/dsdt.asl
+++ b/src/mainboard/amd/torpedo/dsdt.asl
@@ -220,12 +220,12 @@ DefinitionBlock (
PEWD,1
}
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
Scope(\_SB) {
/* PCIe Configuration Space for 16 busses */
@@ -1113,7 +1113,7 @@ DefinitionBlock (
Method(_CRS, 0) {
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
/*
* Declare memory between TOM1 and 4GB as available
* for PCI MMIO.