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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-07 21:42:46 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-23 03:35:58 +0000 |
| commit | 390ba044dcd650e37340f1ddee98bedf1096e76d (patch) | |
| tree | 9836ee3819e8de8f0b5d67150fb19644e118cefe /src/mainboard/amd/torpedo | |
| parent | 14382453349f0ca1c11870ed10f8e7fd839851cc (diff) | |
| download | coreboot-390ba044dcd650e37340f1ddee98bedf1096e76d.tar.xz | |
AGESA binaryPI: Consolidate and fix sleep states
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/amd/torpedo')
| -rw-r--r-- | src/mainboard/amd/torpedo/dsdt.asl | 25 |
1 files changed, 2 insertions, 23 deletions
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index cc830dc973..6947cc2635 100644 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -35,8 +35,6 @@ DefinitionBlock ( Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - /* Some global data */ Name(OSV, Ones) /* Assume nothing */ Name(GPIC, 0x1) /* Assume PIC */ @@ -639,27 +637,8 @@ DefinitionBlock ( } } /* End Scope(_SB) */ - - /* Supported sleep states: */ - Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/common/acpi/sleepstates.asl> /* Wake status package */ Name(WKST,Package(){Zero, Zero}) |