AGESA f12 f15: Add OEM customisation

Follow-up on commits a5d72a3 and 53052fe for f12 and f15.
OEM Hooks are not BiosCallOuts.

Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14888
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

2 files changed, 18 insertions, 78 deletions

diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c
index 19717b1dd4..2293039c25 100644
--- a/src/mainboard/amd/torpedo/OemCustomize.c
+++ b/src/mainboard/amd/torpedo/OemCustomize.c
@@ -18,6 +18,7 @@
 #include <string.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
+#include <PlatformMemoryConfiguration.h>
 
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
 
@@ -161,6 +162,23 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 	return AGESA_SUCCESS;
 }
 
+/*----------------------------------------------------------------------------------------
+ *                        CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+  PSO_END
+};
+
 const struct OEM_HOOK OemCustomize = {
 	.InitEarly = OemInitEarly,
 };
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c
index b42d9a1a45..9abc6512fd 100644
--- a/src/mainboard/amd/torpedo/buildOpts.c
+++ b/src/mainboard/amd/torpedo/buildOpts.c
@@ -236,81 +236,3 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
 #include "GnbInterface.h"
 #include "PlatformInstall.h"
 
-/*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-  //
-  // The following macros are supported (use comma to separate macros):
-  //
-  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-  //      AGESA will base on this value to disable unused MemClk to save power.
-  //      Example:
-  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-  //           Bit AM3/S1g3 pin name
-  //           0   M[B,A]_CLK_H/L[0]
-  //           1   M[B,A]_CLK_H/L[1]
-  //           2   M[B,A]_CLK_H/L[2]
-  //           3   M[B,A]_CLK_H/L[3]
-  //           4   M[B,A]_CLK_H/L[4]
-  //           5   M[B,A]_CLK_H/L[5]
-  //           6   M[B,A]_CLK_H/L[6]
-  //           7   M[B,A]_CLK_H/L[7]
-  //      And platform has the following routing:
-  //           CS0   M[B,A]_CLK_H/L[4]
-  //           CS1   M[B,A]_CLK_H/L[2]
-  //           CS2   M[B,A]_CLK_H/L[3]
-  //           CS3   M[B,A]_CLK_H/L[5]
-  //      Then platform can specify the following macro:
-  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-  //
-  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-  //      AGESA will base on this value to tristate unused CKE to save power.
-  //
-  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-  //      AGESA will base on this value to tristate unused ODT pins to save power.
-  //
-  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-  //      AGESA will base on this value to tristate unused Chip select to save power.
-  //
-  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-  //      Specifies the number of DIMM slots per channel.
-  //
-  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-  //      Specifies the number of Chip selects per channel.
-  //
-  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-  //      Specifies the number of channels per socket.
-  //
-  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-  //
-  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-  //
-  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-  //      Byte6Seed, Byte7Seed, ByteEccSeed)
-  //      Specifies the write leveling seed for a channel of a socket.
-  //
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
-  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
-  PSO_END
-};
-
-/*
- * These tables are optional and may be used to adjust memory timing settings
- */
-#include "mm.h"
-#include "mn.h"