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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:51:00 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-25 20:32:36 +0000 |
commit | 949491979ccec4242fb4398fa954c0678c72cda2 (patch) | |
tree | c027fd568b13c94db005f3220737af285c80e439 /src/mainboard/amd/union_station/romstage.c | |
parent | 6fbf23efc23dcd4a2512759381c24feebf0ed6bf (diff) | |
download | coreboot-949491979ccec4242fb4398fa954c0678c72cda2.tar.xz |
amd/union_station: Switch away from AGESA_LEGACY
Change-Id: I706de64ae5d940df70701c8b9dd717f8e212cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/union_station/romstage.c')
-rw-r--r-- | src/mainboard/amd/union_station/romstage.c | 65 |
1 files changed, 2 insertions, 63 deletions
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 5cd0a8c214..f2b00bc24d 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -13,69 +13,8 @@ * GNU General Public License for more details. */ -#include <lib.h> -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" +#include <northbridge/amd/agesa/state_machine.h> -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x41); - agesawrapper_amdinitenv(); - amd_initenv(); - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ } |