src/mainboard: Fix typo

Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

13 files changed, 14 insertions, 14 deletions

diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 572405d56d..6372c4b5d2 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -29,7 +29,7 @@ static void enable_int_gfx(void)
 
 	volatile u8 *gpio_reg;
 
-	pm_iowrite(0xEA, 0x01);	/* diable the PCIB */
+	pm_iowrite(0xEA, 0x01);	/* disable the PCIB */
 	/* Disable Gec */
 	byte = pm_ioread(0xF6);
 	byte |= 1;
diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c
index dbd6341f23..b647f48129 100644
--- a/src/mainboard/amd/bimini_fam10/resourcemap.c
+++ b/src/mainboard/amd/bimini_fam10/resourcemap.c
@@ -120,7 +120,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/db-ft3b-lc/mptable.c b/src/mainboard/amd/db-ft3b-lc/mptable.c
index 020bc270c3..ebe20ace98 100644
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c
@@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
index 92b4d273f4..7cc635cef4 100644
--- a/src/mainboard/amd/lamar/mptable.c
+++ b/src/mainboard/amd/lamar/mptable.c
@@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v)
 	struct mp_config_table *mc;
 	int bus_isa;
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c
index 95d009ac1e..acdf645a54 100644
--- a/src/mainboard/amd/mahogany_fam10/resourcemap.c
+++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c
@@ -121,7 +121,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index c21e0eac55..95aec3deb9 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -85,7 +85,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  */
 /*
  * Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  * off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index ccf09580b3..9e92ae8e55 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
 	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
 
-	/* Intialize the MP_Table */
+	/* Initialize the MP_Table */
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
 	mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
index fd14a80c42..0e47c52784 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index d0698382dd..1587d32faf 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -18,7 +18,7 @@
 #include <device/device.h>
 
 #include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" 	/* Platform Specific Definitions */
 
 /**
  * Southstation using SB GPIO 17/18 to control the Red/Green LED
diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c
index d696c4dfb3..5a4381424a 100644
--- a/src/mainboard/amd/tilapia_fam10/resourcemap.c
+++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c
@@ -119,7 +119,7 @@ static void setup_mb_resource_map(void)
 		 *	   0 = CPU writes may be posted
 		 *	   1 = CPU writes must be non-posted
 		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h
index 04897f5c24..938de5323e 100644
--- a/src/mainboard/amd/torpedo/gpio.h
+++ b/src/mainboard/amd/torpedo/gpio.h
@@ -298,8 +298,8 @@
 #define GPIO_187_SELECT     FUNCTION2           // USED AS AC LED INDICATOR, LOW ACTIVE
 #define GPIO_188_SELECT     FUNCTION2           // default used AS BATT LED INDICATOR, LOW ACTIVE
                                                 // option for HDMI CEC signal OW ACTIVE
-#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECIEVER, INPUT, low active
-#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
+#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECEIVER, INPUT, low active
+#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERRUPT FROM BATT CHARGER, INPUT
 #define GPIO_191_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, DATA
 #define GPIO_192_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, CLK
 #define GPIO_193_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index 72a97d1322..622fffec39 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -329,7 +329,7 @@
 /**
  *   @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER
  *    @li <b>0</b> - Auto   : Detect Azalia controller automatically.
- *    @li <b>1</b> - Diable : Disable Azalia controller.
+ *    @li <b>1</b> - Disable : Disable Azalia controller.
  *    @li <b>2</b> - Enable : Enable Azalia controller.
  */
 #define INCHIP_AZALIA_CONTROLLER   2
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 8c71fd64fe..7ed27d8041 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -17,7 +17,7 @@
 #include <device/device.h>
 
 #include <southbridge/amd/sb800/sb800.h>
-#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
+#include "SBPLATFORM.h" 	/* Platform Specific Definitions */
 
 /**********************************************
  * Enable the dedicated functions of the board.