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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-02-26 10:11:21 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-08 04:08:00 +0100
commit1b183aa6ce78af27c2e42aa51626f76a4b5d5bb0 (patch)
tree8148c084ef3cdbc6ed86972694864ef910d6668e /src/mainboard/amd
parent3444a9d716ba52f9bd8fb03870442ab1ce1654cf (diff)
downloadcoreboot-1b183aa6ce78af27c2e42aa51626f76a4b5d5bb0.tar.xz
binaryPI boards: Drop any ACPI S3 support
None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18500 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/bettong/mainboard.c3
-rw-r--r--src/mainboard/amd/bettong/romstage.c30
-rw-r--r--src/mainboard/amd/db-ft3b-lc/mainboard.c4
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c34
-rw-r--r--src/mainboard/amd/gardenia/mainboard.c3
-rw-r--r--src/mainboard/amd/gardenia/romstage.c30
-rw-r--r--src/mainboard/amd/lamar/mainboard.c7
-rw-r--r--src/mainboard/amd/lamar/romstage.c31
-rw-r--r--src/mainboard/amd/olivehillplus/mainboard.c4
-rw-r--r--src/mainboard/amd/olivehillplus/romstage.c36
10 files changed, 43 insertions, 139 deletions
diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c
index c31f5b7995..11d6084315 100644
--- a/src/mainboard/amd/bettong/mainboard.c
+++ b/src/mainboard/amd/bettong/mainboard.c
@@ -84,9 +84,6 @@ static void bettong_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 6b12afc83b..29cd8a7284 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +27,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
@@ -63,27 +59,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
- if (s3resume || acpi_is_wakeup_s4()) {
+ if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c
index 6f8742c20a..419a57d8fa 100644
--- a/src/mainboard/amd/db-ft3b-lc/mainboard.c
+++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c
@@ -17,7 +17,6 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
@@ -125,9 +124,6 @@ static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 79cc0f9a42..0ba1c1dfea 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -77,28 +75,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 7ebe087a60..acc9b7cfb9 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
-
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index eca9d3bd58..0136a98344 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -20,7 +20,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
@@ -28,9 +27,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME
- void *resume_backup_memory;
-#endif
amd_initmmio();
hudson_lpc_port80();
@@ -62,27 +58,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /* TODO: Disable cache is not ok. */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /* TODO: Disable cache is not ok. */
+ disable_cache_as_ram();
- if (s3resume || acpi_is_wakeup_s4()) {
+ if (acpi_is_wakeup_s4()) {
outb(0xEE, PM_INDEX);
outb(0x8, PM_DATA);
}
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c
index 25e685b1b8..4e010fc881 100644
--- a/src/mainboard/amd/lamar/mainboard.c
+++ b/src/mainboard/amd/lamar/mainboard.c
@@ -20,7 +20,6 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@@ -147,12 +146,6 @@ static void pirq_setup(void)
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
- /*
- * The mainboard is the first place that we get control in ramstage. Check
- * for S3 resume and call the approriate AGESA/CIMx resume functions.
- */
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index bda8c0fe61..5530a25e84 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -32,7 +31,6 @@
#include <cpu/x86/lapic.h>
#include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
#include "superio/fintek/f81216h/f81216h.h"
@@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- }
- else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
- AGESAWRAPPER(amds3laterestore);
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
- post_code(0x61);
- prepare_for_resume();
- }
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
post_code(0x50);
copy_and_run();
diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c
index 1e82768ddd..8693737aac 100644
--- a/src/mainboard/amd/olivehillplus/mainboard.c
+++ b/src/mainboard/amd/olivehillplus/mainboard.c
@@ -20,7 +20,6 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
@@ -31,9 +30,6 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
- if (acpi_is_wakeup_s3())
- agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 534a8e5d49..c98ae25bc0 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -17,7 +17,6 @@
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
@@ -31,7 +30,6 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-#include <cpu/amd/pi/s3_resume.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -87,29 +85,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
AGESAWRAPPER(amdinitearly);
- int s3resume = acpi_is_wakeup_s3();
- if (!s3resume) {
- post_code(0x40);
- AGESAWRAPPER(amdinitpost);
-
- //PspMboxBiosCmdDramInfo();
- post_code(0x41);
- AGESAWRAPPER(amdinitenv);
- /*
- If code hangs here, please check cahaltasm.S
- */
- disable_cache_as_ram();
- } else { /* S3 detect */
- printk(BIOS_INFO, "S3 detected\n");
-
- post_code(0x60);
- AGESAWRAPPER(amdinitresume);
-
- AGESAWRAPPER(amds3laterestore);
-
- post_code(0x61);
- prepare_for_resume();
- }
+
+ post_code(0x40);
+ AGESAWRAPPER(amdinitpost);
+
+ //PspMboxBiosCmdDramInfo();
+ post_code(0x41);
+ AGESAWRAPPER(amdinitenv);
+ /*
+ If code hangs here, please check cahaltasm.S
+ */
+ disable_cache_as_ram();
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);