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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-12-23 17:20:46 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-12-23 17:20:46 +0000 |
| commit | 33f9633184ddc84151ab3685725d13448cdec232 (patch) | |
| tree | c10a199a36ba2e47da3a8465dc033ce045778a58 /src/mainboard/amd | |
| parent | 5a3c8462dcd0335a0e7f950b9c91af636a727a7a (diff) | |
| download | coreboot-33f9633184ddc84151ab3685725d13448cdec232.tar.xz | |
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
| -rw-r--r-- | src/mainboard/amd/dbm690t/cache_as_ram_auto.c | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/pistachio/cache_as_ram_auto.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c index b691223b6d..6c8d9e3542 100644 --- a/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ b/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -210,6 +210,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); diff --git a/src/mainboard/amd/pistachio/cache_as_ram_auto.c b/src/mainboard/amd/pistachio/cache_as_ram_auto.c index 4ae241a7ef..52b5c0400a 100644 --- a/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ b/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -213,6 +213,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset); post_code(0x06); |