Cleanup Persimmon mainboard whitespace.

Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
author: Marc Jones <marcj303@gmail.com> 2011-11-07 23:26:14 -0700
committer: Stefan Reinauer <stefan.reinauer@coreboot.org> 2011-11-08 19:01:43 +0100
commit: 36abff1dc8e74beafa47ad83de17416681970916 (patch)
tree: 7f9bc41de9ee7c5b400f8268bbec75bab4b44eee /src/mainboard/amd
parent: 19436298711a73d51fa54c76f6004703d25488a5 (diff)
download: coreboot-36abff1dc8e74beafa47ad83de17416681970916.tar.xz
17 files changed, 2081 insertions, 2100 deletions
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
index 3cfd741755..c8379ff16f 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.c
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include "agesawrapper.h"
@@ -26,589 +26,581 @@
 
 STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
-  {AGESA_ALLOCATE_BUFFER,
-   BiosAllocateBuffer
-  },
+	{AGESA_ALLOCATE_BUFFER,
+	 BiosAllocateBuffer
+	},
 
-  {AGESA_DEALLOCATE_BUFFER,
-   BiosDeallocateBuffer
-  },
+	{AGESA_DEALLOCATE_BUFFER,
+	 BiosDeallocateBuffer
+	},
 
-  {AGESA_DO_RESET,
-   BiosReset
-  },
+	{AGESA_DO_RESET,
+	 BiosReset
+	},
 
-  {AGESA_LOCATE_BUFFER,
-   BiosLocateBuffer
-  },
+	{AGESA_LOCATE_BUFFER,
+	 BiosLocateBuffer
+	},
 
-  {AGESA_READ_SPD,
-   BiosReadSpd
-  },
+	{AGESA_READ_SPD,
+	 BiosReadSpd
+	},
 
-  {AGESA_READ_SPD_RECOVERY,
-   BiosDefaultRet
-  },
+	{AGESA_READ_SPD_RECOVERY,
+	 BiosDefaultRet
+	},
 
-  {AGESA_RUNFUNC_ONAP,
-   BiosRunFuncOnAp
-  },
+	{AGESA_RUNFUNC_ONAP,
+	 BiosRunFuncOnAp
+	},
 
-  {AGESA_GNB_PCIE_SLOT_RESET,
-   BiosGnbPcieSlotReset
-  },
+	{AGESA_GNB_PCIE_SLOT_RESET,
+	 BiosGnbPcieSlotReset
+	},
 
-  {AGESA_HOOKBEFORE_DRAM_INIT,
-   BiosHookBeforeDramInit
-  },
+	{AGESA_HOOKBEFORE_DRAM_INIT,
+	 BiosHookBeforeDramInit
+	},
 
-  {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
-   BiosHookBeforeDramInitRecovery
-  },
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+	 BiosHookBeforeDramInitRecovery
+	},
 
-  {AGESA_HOOKBEFORE_DQS_TRAINING,
-   BiosHookBeforeDQSTraining
-  },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,
+	 BiosHookBeforeDQSTraining
+	},
 
-  {AGESA_HOOKBEFORE_EXIT_SELF_REF,
-   BiosHookBeforeExitSelfRefresh
-  },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,
+	 BiosHookBeforeExitSelfRefresh
+	},
 };
 
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINTN i;
-  AGESA_STATUS CalloutStatus;
-  UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
-
-  CalloutStatus = AGESA_UNSUPPORTED;
-
-  for (i = 0; i < CallOutCount; i++)
-  {
-    if (BiosCallouts[i].CalloutName == Func)
-    {
-      CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
-      return CalloutStatus;
-    }
-  }
-
-  return CalloutStatus;
+	UINTN i;
+	AGESA_STATUS CalloutStatus;
+	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+	CalloutStatus = AGESA_UNSUPPORTED;
+
+	for (i = 0; i < CallOutCount; i++) {
+		if (BiosCallouts[i].CalloutName == Func) {
+			CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+			return CalloutStatus;
+		}
+	}
+
+	return CalloutStatus;
 }
 
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AvailableHeapSize;
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              CurrNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              BestFitNodeOffset;
-  UINT32              BestFitPrevNodeOffset;
-  UINT32              NextFreeOffset;
-  BIOS_BUFFER_NODE   *CurrNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *BestFitNodePtr;
-  BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
-  BIOS_BUFFER_NODE   *NextFreePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
-  AllocParams->BufferPointer = NULL;
-
-  AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
-    /* First allocation */
-    CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-    CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
-    CurrNodePtr->BufferSize = AllocParams->BufferLength;
-    CurrNodePtr->NextNodeOffset = 0;
-    AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
-
-    /* Update the remaining free space */
-    FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
-    FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-    FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
-    FreedNodePtr->NextNodeOffset = 0;
-
-    /* Update the offsets for Allocated and Freed nodes */
-    BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
-    BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
-  } else {
-    /* Find out whether BufferHandle has been allocated on the heap. */
-    /* If it has, return AGESA_BOUNDS_CHK */
-    CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-
-    while (CurrNodeOffset != 0) {
-      CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-      if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
-        return AGESA_BOUNDS_CHK;
-      }
-      CurrNodeOffset = CurrNodePtr->NextNodeOffset;
-      /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
-       to the end of the allocated nodes list.
-      */
-
-    }
-    /* Find the node that best fits the requested buffer size */
-    FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-    PrevNodeOffset = FreedNodeOffset;
-    BestFitNodeOffset = 0;
-    BestFitPrevNodeOffset = 0;
-    while (FreedNodeOffset != 0) {
-      FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-      if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        if (BestFitNodeOffset == 0) {
-          /* First node that fits the requested buffer size */
-          BestFitNodeOffset = FreedNodeOffset;
-          BestFitPrevNodeOffset = PrevNodeOffset;
-        } else {
-          /* Find out whether current node is a better fit than the previous nodes */
-          BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-          if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
-            BestFitNodeOffset = FreedNodeOffset;
-            BestFitPrevNodeOffset = PrevNodeOffset;
-          }
-        }
-      }
-      PrevNodeOffset = FreedNodeOffset;
-      FreedNodeOffset = FreedNodePtr->NextNodeOffset;
-    } /* end of while loop */
-
-
-    if (BestFitNodeOffset == 0) {
-      /* If we could not find a node that fits the requested buffer */
-      /* size, return AGESA_BOUNDS_CHK */
-      return AGESA_BOUNDS_CHK;
-    } else {
-      BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-      BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
-
-      /* If BestFitNode is larger than the requested buffer, fragment the node further */
-      if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
-
-        NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
-        NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
-        NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
-      } else {
-        /* Otherwise, next free node is NextNodeOffset of BestFitNode */
-        NextFreeOffset = BestFitNodePtr->NextNodeOffset;
-      }
-
-      /* If BestFitNode is the first buffer in the list, then update
-         StartOfFreedNodes to reflect the new free node
-      */
-      if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
-        BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
-      } else {
-        BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
-      }
-
-      /* Add BestFitNode to the list of Allocated nodes */
-      CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
-      BestFitNodePtr->BufferSize = AllocParams->BufferLength;
-      BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
-      BestFitNodePtr->NextNodeOffset = 0;
-
-      /* Remove BestFitNode from list of Freed nodes */
-      AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
-    }
-  }
-
-  return AGESA_SUCCESS;
+	UINT32				AvailableHeapSize;
+	UINT8				*BiosHeapBaseAddr;
+	UINT32				CurrNodeOffset;
+	UINT32				PrevNodeOffset;
+	UINT32				FreedNodeOffset;
+	UINT32				BestFitNodeOffset;
+	UINT32				BestFitPrevNodeOffset;
+	UINT32				NextFreeOffset;
+	BIOS_BUFFER_NODE	*CurrNodePtr;
+	BIOS_BUFFER_NODE	*FreedNodePtr;
+	BIOS_BUFFER_NODE	*BestFitNodePtr;
+	BIOS_BUFFER_NODE	*BestFitPrevNodePtr;
+	BIOS_BUFFER_NODE	*NextFreePtr;
+	BIOS_HEAP_MANAGER	*BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+	AllocParams->BufferPointer = NULL;
+
+	AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+		/* First allocation */
+		CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+		CurrNodePtr->BufferSize = AllocParams->BufferLength;
+		CurrNodePtr->NextNodeOffset = 0;
+		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+		/* Update the remaining free space */
+		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+		FreedNodePtr->NextNodeOffset = 0;
+
+		/* Update the offsets for Allocated and Freed nodes */
+		BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+		BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+	} else {
+		/* Find out whether BufferHandle has been allocated on the heap. */
+		/* If it has, return AGESA_BOUNDS_CHK */
+		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+		while (CurrNodeOffset != 0) {
+			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+				return AGESA_BOUNDS_CHK;
+			}
+			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+			 to the end of the allocated nodes list.
+			*/
+		}
+		/* Find the node that best fits the requested buffer size */
+		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+		PrevNodeOffset = FreedNodeOffset;
+		BestFitNodeOffset = 0;
+		BestFitPrevNodeOffset = 0;
+		while (FreedNodeOffset != 0) {
+			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				if (BestFitNodeOffset == 0) {
+					/* First node that fits the requested buffer size */
+					BestFitNodeOffset = FreedNodeOffset;
+					BestFitPrevNodeOffset = PrevNodeOffset;
+				} else {
+					/* Find out whether current node is a better fit than the previous nodes */
+					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+						BestFitNodeOffset = FreedNodeOffset;
+						BestFitPrevNodeOffset = PrevNodeOffset;
+					}
+				}
+			}
+			PrevNodeOffset = FreedNodeOffset;
+			FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+		} /* end of while loop */
+
+
+		if (BestFitNodeOffset == 0) {
+			/* If we could not find a node that fits the requested buffer */
+			/* size, return AGESA_BOUNDS_CHK */
+			return AGESA_BOUNDS_CHK;
+		} else {
+			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+			/* If BestFitNode is larger than the requested buffer, fragment the node further */
+			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+			} else {
+				/* Otherwise, next free node is NextNodeOffset of BestFitNode */
+				NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+			}
+
+			/* If BestFitNode is the first buffer in the list, then update
+			 StartOfFreedNodes to reflect the new free node
+			*/
+			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+			} else {
+				BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+			}
+
+			/* Add BestFitNode to the list of Allocated nodes */
+			CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+			BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+			BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+			BestFitNodePtr->NextNodeOffset = 0;
+
+			/* Remove BestFitNode from list of Freed nodes */
+			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+		}
+	}
+
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              AllocNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              NextNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              EndNodeOffset;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_BUFFER_NODE   *PrevNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *NextNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
-
-  /* Find target node to deallocate in list of allocated nodes.
-     Return AGESA_BOUNDS_CHK if the BufferHandle is not found
-  */
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  PrevNodeOffset = AllocNodeOffset;
-
-  while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      return AGESA_BOUNDS_CHK;
-    }
-    PrevNodeOffset = AllocNodeOffset;
-    AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-    AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  }
-
-  /* Remove target node from list of allocated nodes */
-  PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-  PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-
-  /* Zero out the buffer, and clear the BufferHandle */
-  LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
-  AllocNodePtr->BufferHandle = 0;
-  AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
-
-  /* Add deallocated node in order to the list of freed nodes */
-  FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-  FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-
-  EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
-
-  if (AllocNodeOffset < FreedNodeOffset) {
-    /* Add to the start of the freed list */
-    if (EndNodeOffset == FreedNodeOffset) {
-      /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
-      AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
-
-      /* Clear the BufferSize and NextNodeOffset of the previous first node */
-      FreedNodePtr->BufferSize = 0;
-      FreedNodePtr->NextNodeOffset = 0;
-
-    } else {
-      /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the
-         size of BIOS_BUFFER_NODE
-      */
-      AllocNodePtr->NextNodeOffset = FreedNodeOffset;
-    }
-    /* Update StartOfFreedNodes to the new first node */
-    BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
-  } else {
-    /* Traverse list of freed nodes to find where the deallocated node
-       should be place
-    */
-    NextNodeOffset = FreedNodeOffset;
-    NextNodePtr = FreedNodePtr;
-    while (AllocNodeOffset > NextNodeOffset) {
-      PrevNodeOffset = NextNodeOffset;
-      if (NextNodePtr->NextNodeOffset == 0) {
-        break;
-      }
-      NextNodeOffset = NextNodePtr->NextNodeOffset;
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-    }
-
-    /* If deallocated node is adjacent to the next node,
-       concatenate both nodes
-    */
-    if (NextNodeOffset == EndNodeOffset) {
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-      AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
-
-      NextNodePtr->BufferSize = 0;
-      NextNodePtr->NextNodeOffset = 0;
-    } else {
-      /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
-      AllocNodePtr->NextNodeOffset = NextNodeOffset;
-    }
-    /* If deallocated node is adjacent to the previous node,
-       concatenate both nodes
-    */
-    PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-    EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
-    if (AllocNodeOffset == EndNodeOffset) {
-      PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-      PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
-
-      AllocNodePtr->BufferSize = 0;
-      AllocNodePtr->NextNodeOffset = 0;
-    } else {
-      PrevNodePtr->NextNodeOffset = AllocNodeOffset;
-    }
-  }
-  return AGESA_SUCCESS;
+	UINT8				 *BiosHeapBaseAddr;
+	UINT32				AllocNodeOffset;
+	UINT32				PrevNodeOffset;
+	UINT32				NextNodeOffset;
+	UINT32				FreedNodeOffset;
+	UINT32				EndNodeOffset;
+	BIOS_BUFFER_NODE	 *AllocNodePtr;
+	BIOS_BUFFER_NODE	 *PrevNodePtr;
+	BIOS_BUFFER_NODE	 *FreedNodePtr;
+	BIOS_BUFFER_NODE	 *NextNodePtr;
+	BIOS_HEAP_MANAGER	*BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	/* Find target node to deallocate in list of allocated nodes.
+	 Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+	*/
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	PrevNodeOffset = AllocNodeOffset;
+
+	while (AllocNodePtr->BufferHandle !=	AllocParams->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			return AGESA_BOUNDS_CHK;
+		}
+		PrevNodeOffset = AllocNodeOffset;
+		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	}
+
+	/* Remove target node from list of allocated nodes */
+	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+	/* Zero out the buffer, and clear the BufferHandle */
+	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	AllocNodePtr->BufferHandle = 0;
+	AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+	/* Add deallocated node in order to the list of freed nodes */
+	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+	if (AllocNodeOffset < FreedNodeOffset) {
+		/* Add to the start of the freed list */
+		if (EndNodeOffset == FreedNodeOffset) {
+			/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+			AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+			/* Clear the BufferSize and NextNodeOffset of the previous first node */
+			FreedNodePtr->BufferSize = 0;
+			FreedNodePtr->NextNodeOffset = 0;
+		} else {
+			/* Otherwise, add freed node to the start of the list
+			 Update NextNodeOffset and BufferSize to include the
+			 size of BIOS_BUFFER_NODE
+			*/
+			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+		}
+		/* Update StartOfFreedNodes to the new first node */
+		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+	} else {
+		/* Traverse list of freed nodes to find where the deallocated node
+			 should be place
+		*/
+		NextNodeOffset = FreedNodeOffset;
+		NextNodePtr = FreedNodePtr;
+		while (AllocNodeOffset > NextNodeOffset) {
+			PrevNodeOffset = NextNodeOffset;
+			if (NextNodePtr->NextNodeOffset == 0) {
+			break;
+			}
+			NextNodeOffset = NextNodePtr->NextNodeOffset;
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+		}
+
+		/* If deallocated node is adjacent to the next node,
+			 concatenate both nodes
+		*/
+		if (NextNodeOffset == EndNodeOffset) {
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+			NextNodePtr->BufferSize = 0;
+			NextNodePtr->NextNodeOffset = 0;
+		} else {
+			/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+			AllocNodePtr->NextNodeOffset = NextNodeOffset;
+		}
+		/* If deallocated node is adjacent to the previous node,
+			 concatenate both nodes
+		*/
+		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+		if (AllocNodeOffset == EndNodeOffset) {
+			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+			AllocNodePtr->BufferSize = 0;
+			AllocNodePtr->NextNodeOffset = 0;
+		} else {
+			PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+		}
+	}
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AllocNodeOffset;
-  UINT8               *BiosHeapBaseAddr;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
+	UINT32				AllocNodeOffset;
+	UINT8				*BiosHeapBaseAddr;
+	BIOS_BUFFER_NODE	*AllocNodePtr;
+	BIOS_HEAP_MANAGER	*BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS	*AllocParams;
 
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
 
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
 
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
 
-  while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      AllocParams->BufferPointer = NULL;
-      AllocParams->BufferLength = 0;
-      return AGESA_BOUNDS_CHK;
-    } else {
-      AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-      AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-    }
-  }
+	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			AllocParams->BufferPointer = NULL;
+			AllocParams->BufferLength = 0;
+			return AGESA_BOUNDS_CHK;
+		} else {
+			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		}
+	}
 
-  AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
-  AllocParams->BufferLength = AllocNodePtr->BufferSize;
+	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+	AllocParams->BufferLength = AllocNodePtr->BufferSize;
 
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 
 }
 
 AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
+	AGESA_STATUS		Status;
 
-  Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
-  return Status;
+	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
+	return Status;
 }
 
 AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
-  UINT8                 Value;
-  UINTN               ResetType;
-  AMD_CONFIG_PARAMS   *StdHeader;
-
-  ResetType = Data;
-  StdHeader = ConfigPtr;
-
-  //
-  // Perform the RESET based upon the ResetType. In case of
-  // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
-  // AmdResetManager. During the critical condition, where reset is required
-  // immediately, the reset will be invoked directly by writing 0x04 to port
-  // 0xCF9 (Reset Port).
-  //
-  switch (ResetType) {
-  case WARM_RESET_WHENEVER:
-  case COLD_RESET_WHENEVER:
-    break;
-
-  case WARM_RESET_IMMEDIATELY:
-  case COLD_RESET_IMMEDIATELY:
-      Value = 0x06;
-      LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
-    break;
-
-  default:
-    break;
-  }
-
-  Status = 0;
-  return Status;
+	AGESA_STATUS		Status;
+	UINT8				 Value;
+	UINTN				 ResetType;
+	AMD_CONFIG_PARAMS	 *StdHeader;
+
+	ResetType = Data;
+	StdHeader = ConfigPtr;
+
+	//
+	// Perform the RESET based upon the ResetType. In case of
+	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+	// AmdResetManager. During the critical condition, where reset is required
+	// immediately, the reset will be invoked directly by writing 0x04 to port
+	// 0xCF9 (Reset Port).
+	//
+	switch (ResetType) {
+		case WARM_RESET_WHENEVER:
+		case COLD_RESET_WHENEVER:
+		break;
+
+		case WARM_RESET_IMMEDIATELY:
+		case COLD_RESET_IMMEDIATELY:
+			Value = 0x06;
+			LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+		break;
+
+		default:
+		break;
+	}
+
+	Status = 0;
+	return Status;
 }
 
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
+	AGESA_STATUS Status;
+	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
 
-  return Status;
+	return Status;
 }
 
 AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_UNSUPPORTED;
+	return AGESA_UNSUPPORTED;
 }
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
-
-  FcnData = Data;
-  MemData = ConfigPtr;
-
-  Status  = AGESA_SUCCESS;
-  /* Get SB MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  return Status;
+	AGESA_STATUS		Status;
+	UINTN			 FcnData;
+	MEM_DATA_STRUCT	 *MemData;
+	UINT32			AcpiMmioAddr;
+	UINT32			GpioMmioAddr;
+	UINT8			 Data8;
+	UINT16			Data16;
+	UINT8			 TempData8;
+
+	FcnData = Data;
+	MemData = ConfigPtr;
+
+	Status	= AGESA_SUCCESS;
+	/* Get SB MMIO Base (AcpiMmioAddr) */
+	WriteIo8 (0xCD6, 0x27);
+	Data8	 = ReadIo8(0xCD7);
+	Data16	= Data8<<8;
+	WriteIo8 (0xCD6, 0x26);
+	Data8	 = ReadIo8(0xCD7);
+	Data16	|= Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8	= Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	switch(MemData->ParameterListPtr->DDR3Voltage){
+	case VOLT1_35:
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 =	Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	return Status;
 }
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  UINTN                 FcnData;
-  PCIe_SLOT_RESET_INFO  *ResetInfo;
-
-  UINT32  GpioMmioAddr;
-  UINT32  AcpiMmioAddr;
-  UINT8   Data8;
-  UINT16  Data16;
-
-  FcnData   = Data;
-  ResetInfo = ConfigPtr;
-  // Get SB800 MMIO Base (AcpiMmioAddr)
-  WriteIo8(0xCD6, 0x27);
-  Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
-  WriteIo8(0xCD6, 0x26);
-  Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  Status = AGESA_UNSUPPORTED;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  switch (ResetInfo->ResetId)
-  {
-  case 4:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 6:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 7:
-      switch (ResetInfo->ResetControl)
-      {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  }
-  return  Status;
+	AGESA_STATUS Status;
+	UINTN					FcnData;
+	PCIe_SLOT_RESET_INFO	*ResetInfo;
+
+	UINT32	GpioMmioAddr;
+	UINT32	AcpiMmioAddr;
+	UINT8	 Data8;
+	UINT16	Data16;
+
+	FcnData = Data;
+	ResetInfo = ConfigPtr;
+	// Get SB800 MMIO Base (AcpiMmioAddr)
+	WriteIo8(0xCD6, 0x27);
+	Data8 = ReadIo8(0xCD7);
+	Data16=Data8<<8;
+	WriteIo8(0xCD6, 0x26);
+	Data8 = ReadIo8(0xCD7);
+	Data16|=Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	Status = AGESA_UNSUPPORTED;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	switch (ResetInfo->ResetId)
+	{
+	case 4:
+		switch (ResetInfo->ResetControl) {
+			case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 &= ~(UINT8)BIT6 ;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);	 // MXM_GPIO0. GPIO21
+			Status = AGESA_SUCCESS;
+			break;
+			case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 |= BIT6 ;
+			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);		 // MXM_GPIO0. GPIO21
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 6:
+		switch (ResetInfo->ResetControl) {
+			case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 &= ~(UINT8)BIT6 ;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);	 // PCIE_RST#_LAN, GPIO25
+			Status = AGESA_SUCCESS;
+			break;
+			case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6 ;
+			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);		 // PCIE_RST#_LAN, GPIO25
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	case 7:
+		switch (ResetInfo->ResetControl) {
+			case AssertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 &= ~(UINT8)BIT6 ;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);	 // MPCIE_RST0, GPIO02
+			Status = AGESA_SUCCESS;
+			break;
+			case DeassertSlotReset:
+			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 |= BIT6 ;
+			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);		 // MPCIE_RST0, GPIO02
+			Status = AGESA_SUCCESS;
+			break;
+		}
+		break;
+	}
+	return	Status;
 }
diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index b7c78830b4..e023e38d7c 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #ifndef _BIOS_CALLOUT_H_
@@ -23,20 +23,20 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
-#define BIOS_HEAP_START_ADDRESS  0x00010000
-#define BIOS_HEAP_SIZE       0x20000   /* 64MB */
+#define REQUIRED_CALLOUTS			12
+#define BIOS_HEAP_START_ADDRESS		0x00010000
+#define BIOS_HEAP_SIZE				0x20000		/* 64MB */
 
 typedef struct _BIOS_HEAP_MANAGER {
-  //UINT32 AvailableSize;
-  UINT32 StartOfAllocatedNodes;
-  UINT32 StartOfFreedNodes;
+	//UINT32 AvailableSize;
+	UINT32 StartOfAllocatedNodes;
+	UINT32 StartOfFreedNodes;
 } BIOS_HEAP_MANAGER;
 
 typedef struct _BIOS_BUFFER_NODE {
-  UINT32 BufferHandle;
-  UINT32 BufferSize;
-  UINT32 NextNodeOffset;
+	UINT32 BufferHandle;
+	UINT32 BufferSize;
+	UINT32 NextNodeOffset;
 } BIOS_BUFFER_NODE;
 /*
  * CALLOUTS
@@ -54,27 +54,27 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
 /* AGESA ADVANCED CALLOUTS - MEMORY */
-AGESA_STATUS BiosReadSpd (UINT32  Func,UINT32  Data,VOID *ConfigPtr);
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32	Data,VOID *ConfigPtr);
 
 /* BIOS DEFAULT RET */
 AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-/*  Call the host environment interface to provide a user hook opportunity. */
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-#define SB_GPIO_REG02   2
-#define SB_GPIO_REG09   9
-#define SB_GPIO_REG10   10
-#define SB_GPIO_REG15   15
-#define SB_GPIO_REG17   17
-#define SB_GPIO_REG21   21
-#define SB_GPIO_REG25   25
-#define SB_GPIO_REG28   28
+#define SB_GPIO_REG02	2
+#define SB_GPIO_REG09	9
+#define SB_GPIO_REG10	10
+#define SB_GPIO_REG15	15
+#define SB_GPIO_REG17	17
+#define SB_GPIO_REG21	21
+#define SB_GPIO_REG25	25
+#define SB_GPIO_REG28	28
 #endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index 93b4554670..e01e10121f 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -9,132 +9,130 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
 #
 
 if BOARD_AMD_PERSIMMON
 
 config BOARD_SPECIFIC_OPTIONS # dummy
-        def_bool y
-  select ARCH_X86
-  select CPU_AMD_AGESA_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_SB800
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_AGESA_FAMILY14
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14
+	select SOUTHBRIDGE_AMD_CIMX_SB800
 	select SUPERIO_FINTEK_F81865F
-  select BOARD_HAS_FADT
-        select HAVE_BUS_CONFIG
-        select HAVE_OPTION_TABLE
-        select HAVE_PIRQ_TABLE
-        select HAVE_MP_TABLE
-        select HAVE_MAINBOARD_RESOURCES
-        select HAVE_HARD_RESET
-        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        select LIFT_BSP_APIC_ID
-  select SERIAL_CPU_INIT
-  select AMDMCT
-        select HAVE_ACPI_TABLES
-  select BOARD_ROMSIZE_KB_4096
-        select GFXUMA
+	select BOARD_HAS_FADT
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_4096
+	select GFXUMA
 
 config AMD_AGESA
-        bool
-        default y
+	bool
+	default y
 
 config MAINBOARD_DIR
-        string
-        default amd/persimmon
+	string
+	default amd/persimmon
 
 config APIC_ID_OFFSET
-        hex
-        default 0x0
+	hex
+	default 0x0
 
 config MAINBOARD_PART_NUMBER
-        string
-        default "Persimmon"
+	string
+	default "Persimmon"
 
 config HW_MEM_HOLE_SIZEK
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config MAX_CPUS
-        int
-        default 2
+	int
+	default 2
 
 config MAX_PHYSICAL_CPUS
-        int
-        default 1
+	int
+	default 1
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-        bool
-        default n
+	bool
+	default n
 
 config MEM_TRAIN_SEQ
-        int
-        default 2
+	int
+	default 2
 
 config IRQ_SLOT_COUNT
-        int
-        default 11
+	int
+	default 11
 
 config RAMTOP
-        hex
-        default 0x1000000
+	hex
+	default 0x1000000
 
 config HEAP_SIZE
-        hex
-        default 0xc0000
+	hex
+	default 0xc0000
 
 config STACK_SIZE
-        hex
-        default 0x10000
+	hex
+	default 0x10000
 
 config ACPI_SSDTX_NUM
-        int
-        default 0
+	int
+	default 0
 
 config RAMBASE
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config SIO_PORT
-        hex
-        default 0x4e
+	hex
+	default 0x4e
 
 config ONBOARD_VGA_IS_PRIMARY
-        bool
-        default y
+	bool
+	default y
 
 config VGA_BIOS
-       bool
-       default n
+	bool
+	default n
 
 #config VGA_BIOS_FILE
-#        string "VGA BIOS path and filename"
-#        depends on VGA_BIOS
-#        default "rom/video/OntarioGenericVbios.bin"
+#	string "VGA BIOS path and filename"
+#	depends on VGA_BIOS
+#	default "rom/video/OntarioGenericVbios.bin"
 
 config VGA_BIOS_ID
-        string
-        default "1002,9802"
-
+	string
+	default "1002,9802"
 
 config SB800_AHCI_ROM
-        bool
-        default n
+	bool
+	default n
 
 config DRIVERS_PS2_KEYBOARD
-        bool
-        default n
+	bool
+	default n
 
 config WARNINGS_ARE_ERRORS
-        bool
-        default n
+	bool
+	default n
 
 endif # BOARD_AMD_PERSIMMON
-
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
index b0389b82d9..5e37f51205 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
  */
 
 #include "AGESA.h"
@@ -28,141 +28,141 @@
 
 /*---------------------------------------------------------------------------------------*/
 /**
- *  OemCustomizeInitEarly
+ *	OemCustomizeInitEarly
  *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
+ *	Description:
+ *	This is the stub function will call the host environment through the binary block
+ *	interface (call-out port) to provide a user hook opportunity
  *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
+ *	Parameters:
+ *	@param[in]		**PeiServices
+ *	@param[in]		*InitEarly
  *
- *    @retval         VOID
+ *	@retval		 VOID
  *
  **/
 /*---------------------------------------------------------------------------------------*/
 VOID
 OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  )
+	IN	OUT AMD_EARLY_PARAMS	*InitEarly
+	)
 {
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
+	AGESA_STATUS		 Status;
+	VOID				 *BrazosPcieComplexListPtr;
+	VOID				 *BrazosPciePortPtr;
+	VOID				 *BrazosPcieDdiPtr;
 
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
 PCIe_PORT_DESCRIPTOR PortList [] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-        },
+		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+		{
+			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+		},
 	#if 1
-        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-        },
+		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+		{
+			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+		{
+			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+		{
+			0,
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+		},
 	#endif
-        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }
+		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+		}
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
-        {
-          0,   //Descriptor flags
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
-          {ConnectorTypeDP, Aux1, Hdp1}
-        },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
-          {ConnectorTypeDP, Aux2, Hdp2}
-        }
+		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+		{
+			0,	 //Descriptor flags
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+			{ConnectorTypeDP, Aux1, Hdp1}
+		},
+		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+			{ConnectorTypeDP, Aux2, Hdp2}
+		}
 };
 
 PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
+		DESCRIPTOR_TERMINATE_LIST,
+		0,
+		&PortList[0],
+		&DdiList[0]
 };
 
-  // GNB PCIe topology Porting
+	// GNB PCIe topology Porting
 
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
-                                         sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
+	//
+	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	//
+	AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)	+
+										 sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+										 sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
 
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-  if ( Status!= AGESA_SUCCESS) {
-    // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE);
-    return;
-  }
+	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+	if ( Status!= AGESA_SUCCESS) {
+	// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	ASSERT(FALSE);
+	return;
+	}
 
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
-  AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+	AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 
-  AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
+	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
-  LibAmdMemFill (BrazosPcieComplexListPtr,
-                   0,
-                   sizeof (PCIe_COMPLEX_DESCRIPTOR),
-                   &InitEarly->StdHeader);
+	LibAmdMemFill (BrazosPcieComplexListPtr,
+					 0,
+					 sizeof (PCIe_COMPLEX_DESCRIPTOR),
+					 &InitEarly->StdHeader);
 
-  LibAmdMemFill (BrazosPciePortPtr,
-                   0,
-                   sizeof (PCIe_PORT_DESCRIPTOR) * 5,
-                   &InitEarly->StdHeader);
+	LibAmdMemFill (BrazosPciePortPtr,
+					 0,
+					 sizeof (PCIe_PORT_DESCRIPTOR) * 5,
+					 &InitEarly->StdHeader);
 
-  LibAmdMemFill (BrazosPcieDdiPtr,
-                   0,
-                   sizeof (PCIe_DDI_DESCRIPTOR) * 2,
-                   &InitEarly->StdHeader);
+	LibAmdMemFill (BrazosPcieDdiPtr,
+					 0,
+					 sizeof (PCIe_DDI_DESCRIPTOR) * 2,
+					 &InitEarly->StdHeader);
 
-  LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
+	LibAmdMemCopy	(BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+	LibAmdMemCopy	(BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
+	LibAmdMemCopy	(BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
 
 
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
 }
 
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
index b51089f7f6..b50cb1a371 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
  */
 
 #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
@@ -25,48 +25,48 @@
 #include "amdlib.h"
 
 //GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+#define GNB_GPP_PORT4_PORT_PRESENT		1	//0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+#define GNB_GPP_PORT5_PORT_PRESENT		1	//0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+#define GNB_GPP_PORT6_PORT_PRESENT		1	//0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+#define GNB_GPP_PORT7_PORT_PRESENT		1	//0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+#define GNB_GPP_PORT8_PORT_PRESENT		1	//0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
 
 VOID
 OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  );
+	IN	OUT AMD_EARLY_PARAMS	*InitEarly
+	);
 
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c
index 7c5aa390df..637a304cef 100644
--- a/src/mainboard/amd/persimmon/acpi_tables.c
+++ b/src/mainboard/amd/persimmon/acpi_tables.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include <console/console.h>
@@ -35,15 +35,15 @@
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+	if ((i & 0xf) == 0) {
+		printk(BIOS_DEBUG, "\n%08x:", i);
+	}
+	printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -52,193 +52,194 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  /* create all subtables for processors */
-  current = acpi_create_madt_lapics(current);
-
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-             IO_APIC_ADDR, 0);
-
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 9, 9, 0xF);
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
-
-  /* create all subtables for processors */
-  /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-  /* 1: LINT1 connect to NMI */
-
-  return current;
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 9, 9, 0xF);
+
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FDAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
-
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy((void *)current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy((void *)current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy((void *)current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:	* DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+	memcpy((void *)current, srat, srat->header.length);
+	srat = (acpi_srat_t *) current;
+	//acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	 * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+	memcpy((void *)current, slit, slit->header.length);
+	slit = (acpi_slit_t *) current;
+	//acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:	* SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	}
+	else {
+		ssdt = (acpi_header_t *) current;
+		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+		current += ssdt->length;
+		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+		 /* recalculate checksum */
+		ssdt->checksum = 0;
+		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:	* SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 9d9f864141..89f171b079 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -9,16 +9,16 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 /*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
+ *							 M O D U L E S	U S E D
  *----------------------------------------------------------------------------------------
  */
 
@@ -41,501 +41,500 @@
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
 /*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
+ *					 D E F I N I T I O N S	A N D	M A C R O S
  *----------------------------------------------------------------------------------------
  */
 
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
+VOID *DmiTable	= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat	= NULL;
+VOID *AcpiSlit	= NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
+VOID *AcpiAlib	= NULL;
 
 /*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *					T Y P E D E F S	 A N D	 S T R U C T U	R E S
  *----------------------------------------------------------------------------------------
  */
 
 /*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *			 P R O T O T Y P E S	 O F	 L O C A L	 F U	N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 
 /*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
+ *							E X P O R T E D	F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 
 /*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
+ *							L O C A L	F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /* Enable legacy video routing: D18F1xF4 VGA Enable */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
-  PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-   * set to non-posted regions.
-   */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-  PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Map the remaining PCI hole as posted MMIO */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Send all IO (0000-FFFF) to southbridge. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000003;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS				Status;
+	UINT64						MsrReg;
+	UINT32						PciData;
+	PCI_ADDR					PciAddress;
+	AMD_CONFIG_PARAMS			StdHeader;
+
+	/* Enable legacy video routing: D18F1xF4 VGA Enable */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciData = 1;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+	 * set to non-posted regions.
+	 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+	PciData |= 1 << 7;	// set NP (non-posted) bit
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Map the remaining PCI hole as posted MMIO */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00FECF00; // last address before non-posted range
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Send all IO (0000-FFFF) to southbridge. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000003;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  UINT8                         BusRangeVal = 0;
-  UINT8                         BusNum;
-  UINT8                         Index;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-
-  for (Index = 0; Index < 8; Index++) {
-    BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
-    if (BusNum == 1) {
-      BusRangeVal = Index;
-      break;
-    }
-  }
-
-  MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000ull;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS				Status;
+	UINT64						MsrReg;
+	UINT32						PciData;
+	PCI_ADDR					PciAddress;
+	AMD_CONFIG_PARAMS			StdHeader;
+
+	UINT8						BusRangeVal = 0;
+	UINT8						BusNum;
+	UINT8						Index;
+
+	/*
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
+	*/
+
+	for (Index = 0; Index < 8; Index++) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1) {
+			BusRangeVal = Index;
+			break;
+		}
+	}
+
+	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000ull;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+				 0,
+				 sizeof (AMD_INTERFACE_PARAMS),
+				 &(AmdParamStruct.StdHeader));
+
+	LibAmdMemFill (&AmdResetParams,
+				 0,
+				 sizeof (AMD_RESET_PARAMS),
+				 &(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+				 0,
+				 sizeof (AMD_INTERFACE_PARAMS),
+				 &(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32			*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER	*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+				 0,
+				 sizeof (AMD_INTERFACE_PARAMS),
+				 &(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+				 0,
+				 sizeof (AMD_INTERFACE_PARAMS),
+				 &(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+	 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-    case PICK_PSTATE:
-      return AcpiPstate;
-    case PICK_SRAT:
-      return AcpiSrat;
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+				 0,
+				 sizeof (AMD_INTERFACE_PARAMS),
+				 &(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams.DmiTable;
-  AcpiPstate  = AmdLateParams.AcpiPState;
-  AcpiSrat    = AmdLateParams.AcpiSrat;
-  AcpiSlit    = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+				 0,
+				 sizeof (AMD_LATE_PARAMS),
+				 &(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable	= AmdLateParams.DmiTable;
+	AcpiPstate	= AmdLateParams.AcpiPState;
+	AcpiSrat	= AmdLateParams.AcpiSrat;
+	AcpiSlit	= AmdLateParams.AcpiSlit;
+
+	AcpiWheaMce = AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
+	AcpiAlib	= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func,
-  UINT32 Data,
-  VOID *ConfigPtr
-  )
+	UINT32 Func,
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AP_EXE_PARAMS ApExeParams;
-
-  LibAmdMemFill (&ApExeParams,
-                 0,
-                 sizeof (AP_EXE_PARAMS),
-                 &(ApExeParams.StdHeader));
-
-  ApExeParams.StdHeader.AltImageBasePtr = 0;
-  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  ApExeParams.StdHeader.Func = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.FunctionNumber = Func;
-  ApExeParams.RelatedDataBlock = ConfigPtr;
-
-  Status = AmdLateRunApTask (&ApExeParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AP_EXE_PARAMS ApExeParams;
+
+	LibAmdMemFill (&ApExeParams,
+				 0,
+				 sizeof (AP_EXE_PARAMS),
+				 &(ApExeParams.StdHeader));
+
+	ApExeParams.StdHeader.AltImageBasePtr = 0;
+	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	ApExeParams.StdHeader.Func = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.FunctionNumber = Func;
+	ApExeParams.RelatedDataBlock = ConfigPtr;
+
+	Status = AmdLateRunApTask (&ApExeParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+				 0,
+				 sizeof (EVENT_PARAMS),
+				 &(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }
diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h
index f8d924eb60..7bed570e8c 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.h
+++ b/src/mainboard/amd/persimmon/agesawrapper.h
@@ -9,16 +9,16 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 /*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
+ *						 M O D U L E S		U S E D
  *----------------------------------------------------------------------------------------
  */
 
@@ -30,46 +30,46 @@
 #include "AGESA.h"
 
 /*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
+ *					 D E F I N I T I O N S		A N D		M A C R O S
  *----------------------------------------------------------------------------------------
  */
 /* Define AMD Ontario APPU SSID/SVID */
-#define AMD_APU_SVID    0x1022
-#define AMD_APU_SSID    0x1234
-#define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
+#define AMD_APU_SVID		0x1022
+#define AMD_APU_SSID		0x1234
+#define PCIE_BASE_ADDRESS	 CONFIG_MMCONF_BASE_ADDRESS
 
 enum {
-  PICK_DMI,       /* DMI Interface */
-  PICK_PSTATE,    /* Acpi Pstate SSDT Table */
-  PICK_SRAT,      /* SRAT Table */
-  PICK_SLIT,      /* SLIT Table */
-  PICK_WHEA_MCE,  /* WHEA MCE table */
-  PICK_WHEA_CMC,  /* WHEA CMV table */
-  PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+	PICK_DMI,		/* DMI Interface */
+	PICK_PSTATE,	/* Acpi Pstate SSDT Table */
+	PICK_SRAT,		/* SRAT Table */
+	PICK_SLIT,		/* SLIT Table */
+	PICK_WHEA_MCE,	/* WHEA MCE table */
+	PICK_WHEA_CMC,	/* WHEA CMV table */
+	PICK_ALIB,		/* SACPI SSDT table with ALIB implementation */
 };
 
 /*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *					T Y P E D E F S		 A N D		 S T R U C T U	R E S
  *----------------------------------------------------------------------------------------
  */
 
 typedef struct {
-  UINT32 CalloutName;
-  AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+	UINT32 CalloutName;
+	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
 } BIOS_CALLOUT_STRUCT;
 
 /*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *		P R O T O T Y P E S		 O F		 L O C A L		 F U	N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 
 /*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
+ *						E X P O R T E D		F U N C T I O N S
  *----------------------------------------------------------------------------------------
  */
 
 /*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
+ *						L O C A L		F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
 
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 8025f4f91b..368eed2f10 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 /**
@@ -28,32 +28,32 @@
  * For Information about this file, see @ref platforminstall.
  *
  * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 23714 $   @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ * @e project:			AGESA
+ * @e sub-project:	Core
+ * @e \$Revision: 23714 $	 @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
  */
 
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
 
-/*  Select the cpu family.  */
+/*	Select the cpu family.	*/
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*  Select the cpu socket type.  */
-#define INSTALL_G34_SOCKET_SUPPORT  FALSE
-#define INSTALL_C32_SOCKET_SUPPORT  FALSE
+/*	Select the cpu socket type.	*/
+#define INSTALL_G34_SOCKET_SUPPORT	FALSE
+#define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
-#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FP1_SOCKET_SUPPORT  FALSE
-#define INSTALL_FT1_SOCKET_SUPPORT  TRUE
-#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT	FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT	FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT	FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT	TRUE
+#define INSTALL_AM3_SOCKET_SUPPORT	FALSE
 
 /*
  * Agesa optional capabilities selection.
@@ -61,163 +61,163 @@
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
 
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT       TRUE
-#define BLDOPT_REMOVE_FAMILY_12_SUPPORT       TRUE
-#define BLDOPT_REMOVE_FAMILY_14_SUPPORT       FALSE
-#define BLDOPT_REMOVE_FAMILY_15_SUPPORT       TRUE
-
-#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT      FALSE
-#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT      TRUE
-#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
-
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
-#define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
-#define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
-#define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
-#define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
-#define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-#define BLDOPT_REMOVE_SRAT            TRUE
-#define BLDOPT_REMOVE_SLIT            TRUE
-#define BLDOPT_REMOVE_WHEA            TRUE
-#define BLDOPT_REMOVE_DMI             TRUE
-#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-#define BLDOPT_REMOVE_ATM_MODE          TRUE
-//#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
-#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
-//#define BLDOPT_REMOVE_C6_STATE          TRUE
-#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
-#define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT			TRUE
+#define BLDOPT_REMOVE_FAMILY_12_SUPPORT			TRUE
+#define BLDOPT_REMOVE_FAMILY_14_SUPPORT			FALSE
+#define BLDOPT_REMOVE_FAMILY_15_SUPPORT			TRUE
+
+#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT		FALSE
+#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT		TRUE
+
+#define BLDOPT_REMOVE_UDIMMS_SUPPORT			FALSE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT			FALSE
+#define BLDOPT_REMOVE_ECC_SUPPORT				FALSE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE			TRUE
+#define BLDOPT_REMOVE_BANK_INTERLEAVE			FALSE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING			FALSE
+#define BLDOPT_REMOVE_DQS_TRAINING				FALSE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
+	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
+	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
+	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
+	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
+	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
+	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
+#define BLDOPT_REMOVE_SRAT						TRUE
+#define BLDOPT_REMOVE_SLIT						TRUE
+#define BLDOPT_REMOVE_WHEA						TRUE
+#define BLDOPT_REMOVE_DMI						TRUE
+#define BLDOPT_REMOVE_HT_ASSIST					TRUE
+#define BLDOPT_REMOVE_ATM_MODE					TRUE
+//#define BLDOPT_REMOVE_MSG_BASED_C1E			TRUE
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT	TRUE
+#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT		FALSE
+//#define BLDOPT_REMOVE_C6_STATE				TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
+#define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
 
 /*
  * Agesa entry points used in this implementation.
  */
-#define AGESA_ENTRY_INIT_RESET                    TRUE
-#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
-#define AGESA_ENTRY_INIT_EARLY                    TRUE
-#define AGESA_ENTRY_INIT_POST                     TRUE
-#define AGESA_ENTRY_INIT_ENV                      TRUE
-#define AGESA_ENTRY_INIT_MID                      TRUE
-#define AGESA_ENTRY_INIT_LATE                     TRUE
-#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
-#define AGESA_ENTRY_INIT_RESUME                   TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         FALSE
-
-#define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
-
-#define BLDCFG_VRM_CURRENT_LIMIT                24000
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT             0
-#define BLDCFG_VRM_LOW_POWER_THRESHOLD          24000
-#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD       1
-#define BLDCFG_VRM_SLEW_RATE                    5000
-//#define BLDCFG_VRM_NB_SLEW_RATE                 5000
-//#define BLDCFG_VRM_ADDITIONAL_DELAY             0
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY          0
-#define BLDCFG_VRM_HIGH_SPEED_ENABLE            TRUE
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE         FALSE
-#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT         6000
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT      0
-
-//#define BLDCFG_PROCESSOR_SCOPE_NAME0            'C'
-//#define BLDCFG_PROCESSOR_SCOPE_NAME1            '0'
-//#define BLDCFG_PROCESSOR_SCOPE_IN_SB            FALSE
-#define BLDCFG_PLAT_NUM_IO_APICS                3
-//#define BLDCFG_PLATFORM_C1E_MODE                C1eModeDisabled
-//#define BLDCFG_PLATFORM_C1E_OPDATA              0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
-//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
-#define BLDCFG_PLATFORM_CSTATE_MODE             CStateModeC6
-#define BLDCFG_PLATFORM_CSTATE_OPDATA           0x840
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
-//#define BLDCFG_PLATFORM_CPB_MODE                CpbModeAuto
-#define BLDCFG_CORE_LEVELING_MODE               CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST            &OntarioApMtrrSettingsList
-#define BLDCFG_AMD_PLATFORM_TYPE                AMD_PLATFORM_MOBILE
-//#define BLDCFG_STARTING_BUSNUM                  0
-//#define BLDCFG_MAXIMUM_BUSNUM                   0xf8
-//#define BLDCFG_ALLOCATED_BUSNUMS                0x20
-//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST         0
-//#define BLDCFG_BUID_SWAP_LIST                   0
-//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST  0
-//#define BLDCFG_HTFABRIC_LIMITS_LIST             0
-//#define BLDCFG_HTCHAIN_LIMITS_LIST              0
-//#define BLDCFG_BUS_NUMBERS_LIST                 0
-//#define BLDCFG_IGNORE_LINK_LIST                 0
-//#define BLDCFG_LINK_SKIP_REGANG_LIST            0
-//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST       0
-//#define BLDCFG_USE_HT_ASSIST                    TRUE
-//#define BLDCFG_USE_ATM_MODE                     TRUE
-//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE       Nfcm
-#define BLDCFG_S3_LATE_RESTORE                    FALSE
-//#define BLDCFG_USE_32_BYTE_REFRESH              FALSE
-//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY   FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE       Performance
-//#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
-//#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
-//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-#define BLDCFG_CFG_GNB_HD_AUDIO                 FALSE
-//#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
-//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
-//#define BLDCFG_MEM_INIT_PSTATE                  0
-//#define BLDCFG_AMD_PSTATE_CAP_VALUE             0
-#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT       DDR1333_FREQUENCY
-#define BLDCFG_MEMORY_MODE_UNGANGED             TRUE
-//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE         TRUE
-//#define BLDCFG_MEMORY_QUADRANK_TYPE             QUADRANK_UNBUFFERED
-#define BLDCFG_MEMORY_SODIMM_CAPABLE            TRUE
-#define BLDCFG_MEMORY_LRDIMM_CAPABLE            FALSE
-#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
-#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
-#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING      FALSE
-#define BLDCFG_MEMORY_POWER_DOWN                TRUE
-#define BLDCFG_POWER_DOWN_MODE                  POWER_DOWN_BY_CHIP_SELECT
-//#define BLDCFG_ONLINE_SPARE                     FALSE
-//#define BLDCFG_MEMORY_PARITY_ENABLE             FALSE
-#define BLDCFG_BANK_SWIZZLE                     TRUE
-#define BLDCFG_TIMING_MODE_SELECT               TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT              DDR1333_FREQUENCY
-#define BLDCFG_DQS_TRAINING_CONTROL             TRUE
-#define BLDCFG_IGNORE_SPD_CHECKSUM              FALSE
-#define BLDCFG_USE_BURST_MODE                   FALSE
-#define BLDCFG_MEMORY_ALL_CLOCKS_ON             FALSE
-//#define BLDCFG_ENABLE_ECC_FEATURE               TRUE
-//#define BLDCFG_ECC_REDIRECTION                  FALSE
-//#define BLDCFG_SCRUB_DRAM_RATE                  0
-//#define BLDCFG_SCRUB_L2_RATE                    0
-//#define BLDCFG_SCRUB_L3_RATE                    0
-//#define BLDCFG_SCRUB_IC_RATE                    0
-//#define BLDCFG_SCRUB_DC_RATE                    0
-//#define BLDCFG_ECC_SYNC_FLOOD                   0
-//#define BLDCFG_ECC_SYMBOL_SIZE                  0
-//#define BLDCFG_1GB_ALIGN                        FALSE
-#define BLDCFG_UMA_ALLOCATION_MODE              UMA_AUTO
-#define BLDCFG_UMA_ALLOCATION_SIZE              0
-#define BLDCFG_UMA_ABOVE4G_SUPPORT              FALSE
-#define BLDCFG_UMA_ALIGNMENT                    NO_UMA_ALIGNED
-#define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
-#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
+#define AGESA_ENTRY_INIT_RESET					TRUE
+#define AGESA_ENTRY_INIT_RECOVERY				FALSE
+#define AGESA_ENTRY_INIT_EARLY					TRUE
+#define AGESA_ENTRY_INIT_POST					TRUE
+#define AGESA_ENTRY_INIT_ENV					TRUE
+#define AGESA_ENTRY_INIT_MID					TRUE
+#define AGESA_ENTRY_INIT_LATE					TRUE
+#define AGESA_ENTRY_INIT_S3SAVE					TRUE
+#define AGESA_ENTRY_INIT_RESUME					TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE			FALSE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES		FALSE
+
+#define BLDCFG_PCI_MMIO_BASE					CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE					CONFIG_MMCONF_BUS_NUMBER
+
+#define BLDCFG_VRM_CURRENT_LIMIT				24000
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT			0
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD			24000
+#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD		1
+#define BLDCFG_VRM_SLEW_RATE					5000
+//#define BLDCFG_VRM_NB_SLEW_RATE				5000
+//#define BLDCFG_VRM_ADDITIONAL_DELAY			0
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY		0
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE			TRUE
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE		FALSE
+#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT			6000
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT	0
+
+//#define BLDCFG_PROCESSOR_SCOPE_NAME0			'C'
+//#define BLDCFG_PROCESSOR_SCOPE_NAME1			'0'
+//#define BLDCFG_PROCESSOR_SCOPE_IN_SB			FALSE
+#define BLDCFG_PLAT_NUM_IO_APICS				3
+//#define BLDCFG_PLATFORM_C1E_MODE				C1eModeDisabled
+//#define BLDCFG_PLATFORM_C1E_OPDATA			0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1		0
+//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2		0
+#define BLDCFG_PLATFORM_CSTATE_MODE				CStateModeC6
+#define BLDCFG_PLATFORM_CSTATE_OPDATA			0x840
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS	0x840
+//#define BLDCFG_PLATFORM_CPB_MODE				CpbModeAuto
+#define BLDCFG_CORE_LEVELING_MODE				CORE_LEVEL_LOWEST
+#define BLDCFG_AP_MTRR_SETTINGS_LIST			&OntarioApMtrrSettingsList
+#define BLDCFG_AMD_PLATFORM_TYPE				AMD_PLATFORM_MOBILE
+//#define BLDCFG_STARTING_BUSNUM				0
+//#define BLDCFG_MAXIMUM_BUSNUM					0xf8
+//#define BLDCFG_ALLOCATED_BUSNUMS				0x20
+//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST		0
+//#define BLDCFG_BUID_SWAP_LIST					0
+//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST	0
+//#define BLDCFG_HTFABRIC_LIMITS_LIST			0
+//#define BLDCFG_HTCHAIN_LIMITS_LIST			0
+//#define BLDCFG_BUS_NUMBERS_LIST				0
+//#define BLDCFG_IGNORE_LINK_LIST				0
+//#define BLDCFG_LINK_SKIP_REGANG_LIST			0
+//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST		0
+//#define BLDCFG_USE_HT_ASSIST					TRUE
+//#define BLDCFG_USE_ATM_MODE					TRUE
+//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE		Nfcm
+#define BLDCFG_S3_LATE_RESTORE					FALSE
+//#define BLDCFG_USE_32_BYTE_REFRESH			FALSE
+//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY	FALSE
+//#define BLDCFG_PLATFORM_POWER_POLICY_MODE		Performance
+//#define BLDCFG_SET_HTCRC_SYNC_FLOOD			FALSE
+//#define BLDCFG_USE_UNIT_ID_CLUMPING			FALSE
+//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP		0
+#define BLDCFG_CFG_GNB_HD_AUDIO					FALSE
+//#define BLDCFG_CFG_ABM_SUPPORT				FALSE
+//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE		0
+//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL		0
+//#define BLDCFG_MEM_INIT_PSTATE				0
+//#define BLDCFG_AMD_PSTATE_CAP_VALUE			0
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT		DDR1333_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED				TRUE
+//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE		TRUE
+//#define BLDCFG_MEMORY_QUADRANK_TYPE			QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_SODIMM_CAPABLE			TRUE
+#define BLDCFG_MEMORY_LRDIMM_CAPABLE			FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING	TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING	FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING		FALSE
+#define BLDCFG_MEMORY_POWER_DOWN				TRUE
+#define BLDCFG_POWER_DOWN_MODE					POWER_DOWN_BY_CHIP_SELECT
+//#define BLDCFG_ONLINE_SPARE					FALSE
+//#define BLDCFG_MEMORY_PARITY_ENABLE			FALSE
+#define BLDCFG_BANK_SWIZZLE						TRUE
+#define BLDCFG_TIMING_MODE_SELECT				TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT				DDR1333_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL				TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM				FALSE
+#define BLDCFG_USE_BURST_MODE					FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON				FALSE
+//#define BLDCFG_ENABLE_ECC_FEATURE				TRUE
+//#define BLDCFG_ECC_REDIRECTION				FALSE
+//#define BLDCFG_SCRUB_DRAM_RATE				0
+//#define BLDCFG_SCRUB_L2_RATE					0
+//#define BLDCFG_SCRUB_L3_RATE					0
+//#define BLDCFG_SCRUB_IC_RATE					0
+//#define BLDCFG_SCRUB_DC_RATE					0
+//#define BLDCFG_ECC_SYNC_FLOOD					0
+//#define BLDCFG_ECC_SYMBOL_SIZE				0
+//#define BLDCFG_1GB_ALIGN						FALSE
+#define BLDCFG_UMA_ALLOCATION_MODE				UMA_AUTO
+#define BLDCFG_UMA_ALLOCATION_SIZE				0
+#define BLDCFG_UMA_ABOVE4G_SUPPORT				FALSE
+#define BLDCFG_UMA_ALIGNMENT					NO_UMA_ALIGNED
+#define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
+#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
 
 /*
  * Agesa configuration values selection.
@@ -230,21 +230,21 @@
 /* The fixed MTRR values to be set after memory initialization. */
 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 {
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
-  { CPU_LIST_TERMINAL }
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ CPU_LIST_TERMINAL }
 };
 
-/*  Include the files that instantiate the configuration definitions.  */
+/*	Include the files that instantiate the configuration definitions.	*/
 
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
@@ -259,7 +259,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #include "GnbInterface.h"
 
 /*****************************************************************************
- *   Define the RELEASE VERSION string
+ *	 Define the RELEASE VERSION string
  *
  * The Release Version string should identify the next planned release.
  * When a branch is made in preparation for a release, the release manager
@@ -271,123 +271,123 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  * version string as appropriate for the release. The trunk copy of this file
  * should also be updated/incremented for the next expected version, + trailing 'X'
  ****************************************************************************/
-                  // This is the delivery package title, "BrazosPI"
-                  // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+// This is the delivery package title, "BrazosPI"
+// This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING	{'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+// This is the release version number of the AGESA component
+// This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING	{'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
 
 /* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY              200 ///< DDR 400
-#define DDR533_FREQUENCY              266 ///< DDR 533
-#define DDR667_FREQUENCY              333 ///< DDR 667
-#define DDR800_FREQUENCY              400 ///< DDR 800
-#define DDR1066_FREQUENCY             533 ///< DDR 1066
-#define DDR1333_FREQUENCY             667 ///< DDR 1333
-#define DDR1600_FREQUENCY             800 ///< DDR 1600
-#define DDR1866_FREQUENCY             933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY     934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY				200 ///< DDR 400
+#define DDR533_FREQUENCY				266 ///< DDR 533
+#define DDR667_FREQUENCY				333 ///< DDR 667
+#define DDR800_FREQUENCY				400 ///< DDR 800
+#define DDR1066_FREQUENCY				533 ///< DDR 1066
+#define DDR1333_FREQUENCY				667 ///< DDR 1333
+#define DDR1600_FREQUENCY				800 ///< DDR 1600
+#define DDR1866_FREQUENCY				933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY		934 ///< Highest limit of DDR frequency
 
 /* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED             0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED             1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED				0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED				1 ///< Quadrank unbuffered DIMM
 
 /* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO                0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED             1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC            2 ///< Set user specified speed
+#define TIMING_MODE_AUTO				0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED				1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC			2 ///< Set user specified speed
 
 /* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL           0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT       1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL			0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT		1 ///< Chip select power down mode
 
 // The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.  The values below are based on product
+// no clearly defined defaults to be used in the common file.	The values below are based on product
 // and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE            (0)
-#define DFLT_SCRUB_L2_RATE              (0)
-#define DFLT_SCRUB_L3_RATE              (0)
-#define DFLT_SCRUB_IC_RATE              (0)
-#define DFLT_SCRUB_DC_RATE              (0)
-#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE              (5000)
+#define DFLT_SCRUB_DRAM_RATE			(0)
+#define DFLT_SCRUB_L2_RATE				(0)
+#define DFLT_SCRUB_L3_RATE				(0)
+#define DFLT_SCRUB_IC_RATE				(0)
+#define DFLT_SCRUB_DC_RATE				(0)
+#define DFLT_MEMORY_QUADRANK_TYPE		QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE				(5000)
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
 
 /*----------------------------------------------------------------------------------------
- *                        CUSTOMER OVERIDES MEMORY TABLE
+ *						CUSTOMER OVERIDES MEMORY TABLE
  *----------------------------------------------------------------------------------------
  */
 
 /*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
+ *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *	use its default conservative settings.
  */
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-  //
-  // The following macros are supported (use comma to separate macros):
-  //
-  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-  //      AGESA will base on this value to disable unused MemClk to save power.
-  //      Example:
-  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-  //           Bit AM3/S1g3 pin name
-  //           0   M[B,A]_CLK_H/L[0]
-  //           1   M[B,A]_CLK_H/L[1]
-  //           2   M[B,A]_CLK_H/L[2]
-  //           3   M[B,A]_CLK_H/L[3]
-  //           4   M[B,A]_CLK_H/L[4]
-  //           5   M[B,A]_CLK_H/L[5]
-  //           6   M[B,A]_CLK_H/L[6]
-  //           7   M[B,A]_CLK_H/L[7]
-  //      And platform has the following routing:
-  //           CS0   M[B,A]_CLK_H/L[4]
-  //           CS1   M[B,A]_CLK_H/L[2]
-  //           CS2   M[B,A]_CLK_H/L[3]
-  //           CS3   M[B,A]_CLK_H/L[5]
-  //      Then platform can specify the following macro:
-  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-  //
-  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-  //      AGESA will base on this value to tristate unused CKE to save power.
-  //
-  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-  //      AGESA will base on this value to tristate unused ODT pins to save power.
-  //
-  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-  //      AGESA will base on this value to tristate unused Chip select to save power.
-  //
-  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-  //      Specifies the number of DIMM slots per channel.
-  //
-  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-  //      Specifies the number of Chip selects per channel.
-  //
-  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-  //      Specifies the number of channels per socket.
-  //
-  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-  //
-  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-  //
-  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-  //      Byte6Seed, Byte7Seed, ByteEccSeed)
-  //      Specifies the write leveling seed for a channel of a socket.
-  //
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
-  PSO_END
+	//
+	// The following macros are supported (use comma to separate macros):
+	//
+	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+	//			The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+	//			AGESA will base on this value to disable unused MemClk to save power.
+	//			Example:
+	//			BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+	//					 Bit AM3/S1g3 pin name
+	//					 0	 M[B,A]_CLK_H/L[0]
+	//					 1	 M[B,A]_CLK_H/L[1]
+	//					 2	 M[B,A]_CLK_H/L[2]
+	//					 3	 M[B,A]_CLK_H/L[3]
+	//					 4	 M[B,A]_CLK_H/L[4]
+	//					 5	 M[B,A]_CLK_H/L[5]
+	//					 6	 M[B,A]_CLK_H/L[6]
+	//					 7	 M[B,A]_CLK_H/L[7]
+	//			And platform has the following routing:
+	//					 CS0	 M[B,A]_CLK_H/L[4]
+	//					 CS1	 M[B,A]_CLK_H/L[2]
+	//					 CS2	 M[B,A]_CLK_H/L[3]
+	//					 CS3	 M[B,A]_CLK_H/L[5]
+	//			Then platform can specify the following macro:
+	//			MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+	//
+	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+	//			The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+	//			AGESA will base on this value to tristate unused CKE to save power.
+	//
+	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+	//			The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+	//			AGESA will base on this value to tristate unused ODT pins to save power.
+	//
+	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+	//			The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+	//			AGESA will base on this value to tristate unused Chip select to save power.
+	//
+	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+	//			Specifies the number of DIMM slots per channel.
+	//
+	// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+	//			Specifies the number of Chip selects per channel.
+	//
+	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+	//			Specifies the number of channels per socket.
+	//
+	// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+	//			Specifies DDR bus speed of channel ChannelID on socket SocketID.
+	//
+	// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+	//			Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+	//
+	// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+	//			Byte6Seed, Byte7Seed, ByteEccSeed)
+	//			Specifies the write leveling seed for a channel of a socket.
+	//
+	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+	PSO_END
 };
 
 /*
@@ -405,13 +405,13 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
  //
  // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
  //
- //   NOTE:
- //   The following training hardcode values are example values that were taken from a tilapia motherboard
- //   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
- //   the table and replace the byte lane values with your own.
+ //	 NOTE:
+ //	 The following training hardcode values are example values that were taken from a tilapia motherboard
+ //	 with a particular DIMM configuration.	To hardcode your own values, uncomment the appropriate line in
+ //	 the table and replace the byte lane values with your own.
  //
- //                                                                               ------------------ BYTE LANES ----------------------
- //                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+ //	 ------------------ BYTE LANES ----------------------
+ //	BL0	 BL1	 BL2	 BL3	 BL4	 BL5	 BL6	 Bl7	 ECC
  // Write Data Timing
  // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
  // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
@@ -437,22 +437,22 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
  // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
  //--------------------------------------------------------------------------------------------------------------------------------------------------
  // TABLE END
-  NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+	NBACCESS (MTEnd, 0,	0, 0, 0, 0),			// End of Table
 };
 CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
 
 /* ***************************************************************************
- *   Optional User code to be included into the AGESA build
- *    These may be 32-bit call-out routines...
+ *	 Optional User code to be included into the AGESA build
+ *		These may be 32-bit call-out routines...
  */
 //AGESA_STATUS
 //AgesaReadSpd (
-//  IN        UINTN                 FcnData,
-//  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
-//  )
+//	IN				UINTN								 FcnData,
+//	IN OUT		AGESA_READ_SPD_PARAMS *ReadSpd
+//	)
 //{
-//  /* platform code to read an SPD...  */
-//  return Status;
+//	/* platform code to read an SPD...	*/
+//	return Status;
 //}
 
 
diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout
index 8315401c7b..3b98cbb6a1 100644
--- a/src/mainboard/amd/persimmon/cmos.layout
+++ b/src/mainboard/amd/persimmon/cmos.layout
@@ -1,18 +1,18 @@
 #*****************************************************************************
-# 
+#
 #  This file is part of the coreboot project.
-# 
+#
 #  Copyright (C) 2011 Advanced Micro Devices, Inc.
-# 
+#
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
 #  the Free Software Foundation; version 2 of the License.
-# 
+#
 #  This program is distributed in the hope that it will be useful,
 #  but WITHOUT ANY WARRANTY; without even the implied warranty of
 #  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 #  GNU General Public License for more details.
-# 
+#
 #  You should have received a copy of the GNU General Public License
 #  along with this program; if not, write to the Free Software
 #  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index b47e6b9892..e5bbca2b46 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -17,92 +17,91 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 chip northbridge/amd/agesa/family14/root_complex
-        device lapic_cluster 0 on
-                chip cpu/amd/agesa/family14
-                  device lapic 0 on end
-                end
-        end
-        device pci_domain 0 on
-                subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-                                        device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
-                                        device pci 1.1 on end # Internal Multimedia
-                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
-                                        device pci 5.0 off end # PCIE P2P bridge 0x9605
-                                        device pci 6.0 off end # PCIE P2P bridge 0x9606
-                                        device pci 7.0 off end # PCIE P2P bridge 0x9607
-                                        device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa northbridge
+	device lapic_cluster 0 on
+			chip cpu/amd/agesa/family14
+			  device lapic 0 on end
+			end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+			chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+#					device pci 18.0 on #  northbridge
+					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+						device pci 0.0 on end # Root Complex
+						device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+						device pci 1.1 on end # Internal Multimedia
+						device pci 4.0 on end # PCIE P2P bridge 0x9604
+						device pci 5.0 off end # PCIE P2P bridge 0x9605
+						device pci 6.0 off end # PCIE P2P bridge 0x9606
+						device pci 7.0 off end # PCIE P2P bridge 0x9607
+						device pci 8.0 off end # NB/SB Link P2P bridge
+					end # agesa northbridge
 
-                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-                                        device pci 11.0 on end # SATA
-                                        device pci 12.0 on end # USB
-                                        device pci 12.1 on end # USB
-                                        device pci 12.2 on end # USB
-                                        device pci 13.0 on end # USB
-                                        device pci 13.1 on end # USB
-                                        device pci 13.2 on end # USB
-                                        device pci 14.0 on # SM
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end
-                                        end # SM
-                                        device pci 14.1 on end # IDE    0x439c
-                                        device pci 14.2 on end # HDA    0x4383
-                                        device pci 14.3 on # LPC        0x439d
-					        chip superio/fintek/f81865f
-							device pnp 4e.0 off		# Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 4e.3 off end			# Parallel Port
-							device pnp 4e.4 off end			# Hardware Monitor
-							device pnp 4e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 4e.6 off end			# GPIO
-							device pnp 4e.a off end			# PME
-							device pnp 4e.10 on			# COM1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 4e.11 off			# COM2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-                                                end # f81865f
-					end #LPC
-					device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-	  				device pci 14.5 on  end # USB 2
-					device pci 15.0 off end # PCIe PortA
-					device pci 15.1 off end # PCIe PortB
-					device pci 15.2 off end # PCIe PortC
-					device pci 15.3 off end # PCIe PortD
-					device pci 16.0 off end # OHCI USB3
-					device pci 16.2 off end # EHCI USB3
-					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx/sb800
-#                       end #  device pci 18.0
+					chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+						device pci 11.0 on end # SATA
+						device pci 12.0 on end # USB
+						device pci 12.1 on end # USB
+						device pci 12.2 on end # USB
+						device pci 13.0 on end # USB
+						device pci 13.1 on end # USB
+						device pci 13.2 on end # USB
+						device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE	0x439c
+					device pci 14.2 on end # HDA	0x4383
+					device pci 14.3 on # LPC		0x439d
+					chip superio/fintek/f81865f
+						device pnp 4e.0 off		# Floppy
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
+						end
+						device pnp 4e.3 off end			# Parallel Port
+						device pnp 4e.4 off end			# Hardware Monitor
+						device pnp 4e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 4e.6 off end			# GPIO
+						device pnp 4e.a off end			# PME
+						device pnp 4e.10 on			# COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 4e.11 off			# COM2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end # f81865f
+				end #LPC
+				device pci 14.4 on  end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+				device pci 14.5 on  end # USB 2
+				device pci 15.0 off end # PCIe PortA
+				device pci 15.1 off end # PCIe PortB
+				device pci 15.2 off end # PCIe PortC
+				device pci 15.3 off end # PCIe PortD
+				device pci 16.0 off end # OHCI USB3
+				device pci 16.2 off end # EHCI USB3
+				register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+				register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+			end	#southbridge/amd/cimx/sb800
+#			end #  device pci 18.0
 # These seem unnecessary
-                        device pci 18.0 on end
-                        device pci 18.1 on end
-                        device pci 18.2 on end
-                        device pci 18.3 on end
-                        device pci 18.4 on end
-                        device pci 18.5 on end
-                        device pci 18.6 on end
-                        device pci 18.7 on end
-                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-        end #pci_domain
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+	end #pci_domain
 end #northbridge/amd/agesa/family14/root_complex
-
diff --git a/src/mainboard/amd/persimmon/dimmSpd.c b/src/mainboard/amd/persimmon/dimmSpd.c
index 2bd27d6f42..1343ae94e2 100644
--- a/src/mainboard/amd/persimmon/dimmSpd.c
+++ b/src/mainboard/amd/persimmon/dimmSpd.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
  */
 
 #include "Porting.h"
@@ -30,19 +30,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 * SPD address table - porting required
 */
 
-static const UINT8 spdAddressLookup [2] [2] [4] =  // socket, channel, dimm
-   {
-   // socket 0
-      {
-         {0xA0, 0xA2},  // channel 0 dimms
-         {0x00, 0x00},  // channel 1 dimms
-      },
-   // socket 1
-      {
-         {0x00, 0x00},  // channel 0 dimms
-         {0x00, 0x00},  // channel 1 dimms
-      },
-   };
+static const UINT8 spdAddressLookup [2] [2] [4] =	// socket, channel, dimm
+{
+// socket 0
+	{
+		{0xA0, 0xA2},	// channel 0 dimms
+		{0x00, 0x00},	// channel 1 dimms
+	},
+	// socket 1
+	{
+		{0x00, 0x00},	// channel 0 dimms
+		{0x00, 0x00},	// channel 1 dimms
+	},
+};
 
 /*-----------------------------------------------------------------------------
  *
@@ -50,117 +50,114 @@ static const UINT8 spdAddressLookup [2] [2] [4] =  // socket, channel, dimm
  */
 
 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
-   {
-   unsigned int status;
-   UINT64 limit;
-
-   address |= 1; // set read bit
-
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 1, 0x1F);                // clear error status
-   __outbyte (iobase + 3, offset);              // offset in eeprom
-   __outbyte (iobase + 4, address);             // slave address and read bit
-   __outbyte (iobase + 2, 0x48);                // read byte command
-
-   // time limit to avoid hanging for unexpected error status (should never happen)
-   limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
-   }
+{
+	unsigned int status;
+	UINT64 limit;
+
+	address |= 1; // set read bit
+
+	__outbyte (iobase + 0, 0xFF);				// clear error status
+	__outbyte (iobase + 1, 0x1F);				// clear error status
+	__outbyte (iobase + 3, offset);				// offset in eeprom
+	__outbyte (iobase + 4, address);			// slave address and read bit
+	__outbyte (iobase + 2, 0x48);				// read byte command
+
+	// time limit to avoid hanging for unexpected error status (should never happen)
+	limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;		// SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;		// HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;				// check for done with no errors
+	return status;
+}
 
 /*-----------------------------------------------------------------------------
  *
  * readSmbusByte - read a single SPD byte from the default offset
- *                 this function is faster function readSmbusByteData
+ *				 this function is faster function readSmbusByteData
  */
 
 static int readSmbusByte (int iobase, int address, char *buffer)
-   {
-   unsigned int status;
-   UINT64 limit;
-
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 2, 0x44);                // read command
-
-   // time limit to avoid hanging for unexpected error status
-   limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
-   }
+{
+	unsigned int status;
+	UINT64 limit;
+
+	__outbyte (iobase + 0, 0xFF);				// clear error status
+	__outbyte (iobase + 2, 0x44);				// read command
+
+	// time limit to avoid hanging for unexpected error status
+	limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;		// SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;		// HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;				// check for done with no errors
+	return status;
+}
 
 /*---------------------------------------------------------------------------
  *
  * readspd - Read one or more SPD bytes from a DIMM.
- *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid
- *           sending offset for every byte.
- *          Reads 128 bytes in 7-8 ms at 400 KHz.
+ *			Start with offset zero and read sequentially.
+ *			Optimization relies on autoincrement to avoid
+ *			sending offset for every byte.
+ *			Reads 128 bytes in 7-8 ms at 400 KHz.
  */
 
 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
-   {
-   int index, error;
+{
+	int index, error;
 
-   /* read the first byte using offset zero */
-   error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
-   if (error) return error;
+	/* read the first byte using offset zero */
+	error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+	if (error) return error;
 
-   /* read the remaining bytes using auto-increment for speed */
-   for (index = 1; index < count; index++)
-      {
-      error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
-      if (error) return error;
-      }
+	/* read the remaining bytes using auto-increment for speed */
+	for (index = 1; index < count; index++) {
+		error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+		if (error) return error;
+	}
 
-   return 0;
-   }
+	return 0;
+}
 
 static void writePmReg (int reg, int data)
-   {
-   __outbyte (0xCD6, reg);
-   __outbyte (0xCD7, data);
-   }
+	{
+	__outbyte (0xCD6, reg);
+	__outbyte (0xCD7, data);
+	}
 
 static void setupFch (int ioBase)
-   {
-   writePmReg (0x2D, ioBase >> 8);
-   writePmReg (0x2C, ioBase | 1);
-   writePmReg (0x29, 0x80);
-   writePmReg (0x28, 0x61);
-   __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
-   }
+{
+	writePmReg (0x2D, ioBase >> 8);
+	writePmReg (0x2C, ioBase | 1);
+	writePmReg (0x29, 0x80);
+	writePmReg (0x28, 0x61);
+	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+}
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
-   {
-   int spdAddress, ioBase;
-
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
-   if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
-   if (spdAddress == 0) return AGESA_ERROR;
-   ioBase = 0xB00;
-   setupFch (ioBase);
-   return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
-   }
+{
+	int spdAddress, ioBase;
+
+	if (info->SocketId	 >= DIMENSION (spdAddressLookup		)) return AGESA_ERROR;
+	if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]	)) return AGESA_ERROR;
+	if (info->DimmId		>= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+
+	spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+	if (spdAddress == 0) return AGESA_ERROR;
+	ioBase = 0xB00;
+	setupFch (ioBase);
+	return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+}
diff --git a/src/mainboard/amd/persimmon/dimmSpd.h b/src/mainboard/amd/persimmon/dimmSpd.h
index 069c34a6fc..caaefbeab8 100644
--- a/src/mainboard/amd/persimmon/dimmSpd.h
+++ b/src/mainboard/amd/persimmon/dimmSpd.h
@@ -50,10 +50,10 @@
 
 AGESA_STATUS
 AmdMemoryReadSPD (
-  IN UINT32 Func,
-  IN UINT32 Data,
-  IN OUT AGESA_READ_SPD_PARAMS *SpdData
-  );
+	IN UINT32 Func,
+	IN UINT32 Data,
+	IN OUT AGESA_READ_SPD_PARAMS *SpdData
+	);
 
 /*---------------------------------------------------------------------------------------
  *                          L O C A L    F U N C T I O N S
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 2d28023574..0142762c0a 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
  */
 
 #include <console/console.h>
@@ -43,7 +43,7 @@ u32 apicid_sb800;
 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
 */
 u32 pci1234x[] = {
-  0x0000ff0,
+	0x0000ff0,
 };
 
 u32 bus_type[256];
@@ -54,83 +54,80 @@ static u32 get_bus_conf_done = 0;
 
 void get_bus_conf(void)
 {
-  u32 apicid_base;
-  u32 status;
+	u32 apicid_base;
+	u32 status;
 
-  device_t dev;
-  int i, j;
+	device_t dev;
+	int i, j;
 
-  if (get_bus_conf_done == 1)
-    return;   /* do it only once */
+	if (get_bus_conf_done == 1)
+		return;	 /* do it only once */
 
-  get_bus_conf_done = 1;
+	get_bus_conf_done = 1;
 
 /*
- * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+ * This is the call to AmdInitLate.	It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
- * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+ * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
  * after the decision about S3 resume is made, and before the system tables are
- * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
+ * written into RAM.	The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain".	There is no platform
  * specific entry point between the S3 resume decision point and the call to
  * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions.  The first of ose would seem to be the right
+ * the ACPI table write functions.	The first of ose would seem to be the right
  * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written.  This routine is called at the beginning
+ * called before the ACPI tables are written.	This routine is called at the beginning
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate();
-  if(status) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-  }
-
-  sbdn_sb800 = 0;
-
-  for (i = 0; i < 3; i++) {
-    bus_sb800[i] = 0;
-  }
-
-  for (i = 0; i < 256; i++) {
-    bus_type[i] = 0; /* default ISA bus. */
-  }
-
-
-  bus_type[0] = 1;  /* pci */
-
-//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-  bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
-
-  /* sb800 */
-  dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
-
-
-
-  if (dev) {
-    bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-    bus_isa++;
-    for (j = bus_sb800[1]; j < bus_isa; j++)
-      bus_type[j] = 1;
-  }
-
-  for (i = 0; i < 4; i++) {
-    dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
-    if (dev) {
-      bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-      bus_isa++;
-    }
-  }
-  for (j = bus_sb800[2]; j < bus_isa; j++)
-    bus_type[j] = 1;
-
-
-  /* I/O APICs:   APIC ID Version State   Address */
-  bus_isa = 10;
-  apicid_base = CONFIG_MAX_CPUS;
-  apicid_sb800 = apicid_base;
+	status = agesawrapper_amdinitlate();
+	if(status) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+	}
+
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;	/* pci */
+
+//	bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* I/O APICs:	 APIC ID Version State	 Address */
+	bus_isa = 10;
+	apicid_base = CONFIG_MAX_CPUS;
+	apicid_sb800 = apicid_base;
 
 #if CONFIG_AMD_SB_CIMX
 	sb_Late_Post();
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 135f8f458f..3b181a12bf 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -63,14 +63,14 @@ static void persimmon_enable(device_t dev)
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr.lo, msr.hi);
+		(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+		 __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
-	     __func__, msr2.lo, msr2.hi);
+		(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+		 __func__, msr2.lo, msr2.hi);
 
 	/* refer to UMA Size Consideration in Family14h BKDG. */
 	sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
@@ -78,17 +78,16 @@ static void persimmon_enable(device_t dev)
 		uma_memory_size = 0x18000000;	/* >= 2G memory, 384M recommended UMA */
 	}
 	else {
-	  if (sys_mem >= 0x40000000) {
-		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
-	  }
-	  else {
-		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
-	  }
+		if (sys_mem >= 0x40000000) {
+			uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
+		} else {
+			uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
+		}
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
-		    __func__, uma_memory_size, uma_memory_base);
+			__func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
 #else
@@ -105,9 +104,9 @@ int add_mainboard_resources(struct lb_memory *mem)
  	 */
 #if (CONFIG_GFXUMA == 1)
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
-		    uma_memory_base, uma_memory_size);
+			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
-			    uma_memory_size);
+				uma_memory_size);
 #endif
 	return 0;
 }
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 546d9bd393..92c842f8ea 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 
@@ -35,124 +35,124 @@ extern u32 bus_type[256];
 extern u32 sbdn_sb800;
 
 u8 intr_data[] = {
-  [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
-  [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
-  [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x10,0x11,0x12,0x13
 };
 
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;
 
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LAPIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD	 ", 8);
 
-  smp_write_processors(mc);
+	smp_write_processors(mc);
 
-  get_bus_conf();
+	get_bus_conf();
 
-  mptable_write_buses(mc, NULL, &bus_isa);
+	mptable_write_buses(mc, NULL, &bus_isa);
 
-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:	 APIC ID Version State	 Address */
 
-  u32 dword;
-  u8 byte;
+	u32 dword;
+	u8 byte;
 
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword &= 0xFFFFFFF0;
-  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword &= 0xFFFFFFF0;
+	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+	outb(byte | 0x80, 0xC00);
+	outb(intr_data[byte], 0xC01);
+	}
 
-  /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:	Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #if CONFIG_GENERATE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
-  //PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
-  /* HD Audio: */
-  PCI_INT(0x0, 0x14, 0x2, 0x12);
-
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-  /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
-  /* on board NIC & Slot PCIE.  */
-
-  /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
-
-  /* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
-
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
+
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
+
+	/* on board NIC & Slot PCIE.	*/
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+
+	/* PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 0eb7490c6a..bf8535f9f1 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
 #include <stdint.h>
@@ -44,78 +44,77 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  u32 val;
-
-  // all cores: allow caching of flash chip code and data
-  // (there are no cache-as-ram reliability concerns with family 14h)
-  __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
-  __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
-
-  // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
-  __writemsr (0xc0010062, 0);
-
-  if (!cpu_init_detectedx && boot_cpu()) {
-    post_code(0x30);
-    sb_Poweron_Init();
-
-    post_code(0x31);
-    f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-    console_init();
-  }
-
-  /* Halt if there was a built in self test failure */
-  post_code(0x34);
-  report_bist_failure(bist);
-
-  // Load MPB
-  val = cpuid_eax(1);
-  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
-  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
-  post_code(0x35);
-  val = agesawrapper_amdinitmmio();
-
-  post_code(0x37);
-  val = agesawrapper_amdinitreset();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-  }
-
-  post_code(0x38);
-  printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
-  post_code(0x39);
-  val = agesawrapper_amdinitearly ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
-
-  post_code(0x40);
-  val = agesawrapper_amdinitpost ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
-
-  post_code(0x41);
-  val = agesawrapper_amdinitenv ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
-
-  /* Initialize i8259 pic */
-  post_code(0x41);
-  setup_i8259 ();
-
-  /* Initialize i8254 timers */
-  post_code(0x42);
-  setup_i8254 ();
-
-  post_code(0x50);
-  copy_and_run(0);
-
-  post_code(0x54);  // Should never see this post code.
+	u32 val;
+
+	// all cores: allow caching of flash chip code and data
+	// (there are no cache-as-ram reliability concerns with family 14h)
+	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	__writemsr (0xc0010062, 0);
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x30);
+		sb_Poweron_Init();
+
+		post_code(0x31);
+		f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		console_init();
+	}
+
+	/* Halt if there was a built in self test failure */
+	post_code(0x34);
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	post_code(0x35);
+	val = agesawrapper_amdinitmmio();
+
+	post_code(0x37);
+	val = agesawrapper_amdinitreset();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	}
+
+	post_code(0x38);
+	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+	post_code(0x39);
+	val = agesawrapper_amdinitearly ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+	post_code(0x40);
+	val = agesawrapper_amdinitpost ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+	post_code(0x41);
+	val = agesawrapper_amdinitenv ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+	/* Initialize i8259 pic */
+	post_code(0x41);
+	setup_i8259 ();
+
+	/* Initialize i8254 timers */
+	post_code(0x42);
+	setup_i8254 ();
+
+	post_code(0x50);
+	copy_and_run(0);
+
+	post_code(0x54);	// Should never see this post code.
 }
-
author	Marc Jones <marcj303@gmail.com>	2011-11-07 23:26:14 -0700
committer	Stefan Reinauer <stefan.reinauer@coreboot.org>	2011-11-08 19:01:43 +0100
commit	36abff1dc8e74beafa47ad83de17416681970916 (patch)
tree	7f9bc41de9ee7c5b400f8268bbec75bab4b44eee /src/mainboard/amd
parent	19436298711a73d51fa54c76f6004703d25488a5 (diff)
download	coreboot-36abff1dc8e74beafa47ad83de17416681970916.tar.xz