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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:47:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:47:43 +0000
commit64ed2b73451de4b655b3fdda0ff42825a165c317 (patch)
tree0faaae313a9a9edbf8b33f56fc18830ba14aa75f /src/mainboard/amd
parent5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff)
downloadcoreboot-64ed2b73451de4b655b3fdda0ff42825a165c317.tar.xz
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/amd')
-rw-r--r--src/mainboard/amd/dbm690t/romstage.c2
-rw-r--r--src/mainboard/amd/mahogany/romstage.c2
-rw-r--r--src/mainboard/amd/pistachio/romstage.c2
-rw-r--r--src/mainboard/amd/rumba/romstage.c6
-rw-r--r--src/mainboard/amd/serengeti_cheetah/ap_romstage.c2
-rw-r--r--src/mainboard/amd/serengeti_cheetah/romstage.c14
6 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index b46ca394be..3c808d41cb 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index a5991ad1eb..3dc2801546 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index f8b64f1320..6cdaf42df5 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x06);
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index e9b21ed029..813b009471 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -50,7 +50,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* get module banks (sides) per dimm, SPD byte 5 */
module_banks = spd_read_byte(0xA0, 5);
if (module_banks < 1 || module_banks > 2)
- print_err("Module banks per dimm\r\n");
+ print_err("Module banks per dimm\n");
module_banks >>= 1;
msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
@@ -58,7 +58,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* get component banks per module bank, SPD byte 17 */
val = spd_read_byte(0xA0, 17);
if (val < 2 || val > 4)
- print_err("Component banks per module bank\r\n");
+ print_err("Component banks per module bank\n");
val >>= 2;
msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
@@ -78,7 +78,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
print_debug("computed msr.hi ");
print_debug_hex32(msr.hi);
- print_debug("\r\n");
+ print_debug("\n");
msr.lo = 0x00003000;
wrmsr(MC_CF07_DATA, msr);
diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 582e93abc2..c2b8e8c7b3 100644
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -69,7 +69,7 @@ void hardwaremain(int ret_addr)
#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
#else
- print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+ print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
#endif
train_ram(id.nodeid, sysinfo, sysinfox);
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index c46bdf447d..b45e4f6716 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -92,14 +92,14 @@ static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_HUB 0x18
int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+ print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+ print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
#endif
@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
@@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
@@ -276,7 +276,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\r\n");
+ print_info("ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif